S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 84
S71GL256NB0
Manufacturer Part Number
S71GL256NB0
Description
Stacked Multi-chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GL256NB0.pdf
(147 pages)
- Current page: 84 of 147
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AC Characteristics
Hardware Reset (RESET#)
Note:
the RESET# pin needs to be held low only for 100µs for power-up.
84
JEDEC
Parameter
Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated,
CE#, OE#
CE#, OE#
RESET#
RESET#
RY/BY#
RY/BY#
t
t
Std.
Ready
Ready
t
t
t
t
RPD
RH
RB
RP
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
RESET# Pulse Width
Reset High Time Before Read (See Note)
RESET# Low to Standby Mode
RY/BY# Recovery Time
Reset Timings NOT during Embedded Algorithms
t
Ready
t
t
Reset Timings during Embedded Algorithms
RP
RP
S29GLxxxN MirrorBit
Description
Figure 13. Reset Timings
A d v a n c e
t
Ready
t
RH
TM
Flash Family
I n f o r m a t i o n
Max
Max
Min
Min
Min
Min
All Speed Options
t
RB
50
20
1
1
1
0
S29GLxxxN_00_A4 June 14, 2004
Unit
ms
ms
ms
ns
µs
ns
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