S71GL256NB0 SPANSION [SPANSION], S71GL256NB0 Datasheet - Page 95
S71GL256NB0
Manufacturer Part Number
S71GL256NB0
Description
Stacked Multi-chip Product (MCP)
Manufacturer
SPANSION [SPANSION]
Datasheet
1.S71GL256NB0.pdf
(147 pages)
- Current page: 95 of 147
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AC Characteristics
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. D
4. Waveforms are for the word mode.
Latchup Characteristics
Note: Includes all pins except V
June 14, 2004 S29GLxxxN_00_A4
Input voltage with respect to V
(including A9, OE#, and RESET#)
Input voltage with respect to V
V
CC
Current
Addresses
RESET#
RY/BY#
WE#
Data
OE#
CE#
Figure 20. Alternate CE# Controlled Write (Erase/Program)
Description
A d v a n c e
t
RH
555 for program
2AA for erase
SS
SS
CC
on all pins except I/O pins
on all I/O pins
. Test conditions: V
t
t
t
WS
WH
WC
S29GLxxxN MirrorBit
A0 for program
55 for erase
t
GHEL
t
t
t
DS
CP
PA for program
SA for sector erase
555 for chip erase
CPH
I n f o r m a t i o n
t
AS
t
DH
Operation Timings
CC
t
AH
= 3.0 V, one pin at a time.
PD for program
30 for sector erase
10 for chip erase
t
BUSY
TM
Flash Family
OUT
t
WHWH1 or 2
is the data written to the device.
Data# Polling
–100 mA
–1.0 V
–1.0 V
Min
DQ7#
PA
D
OUT
V
+100 mA
CC
12.5 V
Max
+ 1.0 V
95
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