MM74HC4514N Fairchild Semiconductor, MM74HC4514N Datasheet

IC DECODER W/LTCH 4-16LINE 24DIP

MM74HC4514N

Manufacturer Part Number
MM74HC4514N
Description
IC DECODER W/LTCH 4-16LINE 24DIP
Manufacturer
Fairchild Semiconductor
Series
74HCr
Type
Decoderr
Datasheet

Specifications of MM74HC4514N

Circuit
1 x 4:16
Independent Circuits
1
Current - Output High, Low
5.2mA, 5.2mA
Voltage Supply Source
Dual Supply
Voltage - Supply
2 V ~ 6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Through Hole
Package / Case
24-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74HC4514

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MM74HC4514N
Manufacturer:
NS
Quantity:
6 227
© 2003 Fairchild Semiconductor Corporation
MM74HC4514WM
MM74HC4514MTC
MM74HC4514N
MM74HC4514
4-to-16 Line Decoder with Latch
General Description
The MM74HC4514 utilizes advanced silicon-gate CMOS
technology, which is well suited to memory address decod-
ing or data routing application. It possesses high noise
immunity and low power dissipation usually associated with
CMOS circuitry, yet speeds comparable to low power
Schottky TTL circuits. It can drive up to 10 LS-TTL loads.
The MM74HC4514 contain a 4-to-16 line decoder and a 4-
bit latch. The latch can store the data on the select inputs,
thus allowing a selected output to remain HIGH even
though the select data has changed. When the LATCH
ENABLE input to the latches is HIGH the outputs will
change with the inputs. When LATCH ENABLE goes LOW
the data on the select inputs is stored in the latches. The
four select inputs determine which output will go HIGH pro-
vided the INHIBIT input is LOW. If the INHIBIT input is
HIGH all outputs are held LOW thus disabling the decoder.
The MM74HC4514 is functionally and pinout equivalent to
the CD4514BC and the MC1451BC. All inputs are pro-
tected against damage due to static discharge diodes from
V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
CC
Order Number
and ground.
Package Number
MTC24
M24B
N24C
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
DS005215
Features
Typical propagation delay: 18 ns
Low quiescent power: 80 A maximum (74HC Series)
Low input current: 1 A maximum
Fanout of 10 LS-TTL loads (74HC Series)
Package Description
February 1984
Revised July 2003
www.fairchildsemi.com

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MM74HC4514N Summary of contents

Page 1

... Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide MM74HC4514MTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4514N N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagram Top View Logic Diagram www.fairchildsemi.com Truth Table Data Inputs LE Inhibit ...

Page 3

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...

Page 4

AC Electrical Characteristics 5V pF Symbol Parameter Maximum Propagation Delay Data to Output PHL PLH t Maximum Propagation Delay LE to Output ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M24B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC24 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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