GS820E32AGT-133 GSI [GSI Technology], GS820E32AGT-133 Datasheet - Page 10
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GS820E32AGT-133
Manufacturer Part Number
GS820E32AGT-133
Description
64K x 32 2Mb Synchronous Burst SRAM
Manufacturer
GSI [GSI Technology]
Datasheet
1.GS820E32AGT-133.pdf
(21 pages)
Notes:
1.
2.
3.
Rev: 1.07 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
The diagram shows supported (tested) synchronous state transitions, plus supported transitions that depend upon the use of G.
Use of “Dummy Reads” (Read Cycles with G high) may be used to make the transition from Read cycles to Write cycles without passing
through a Deselect cycle. Dummy Read cycles increment the address counter just like normal Read cycles.
Transitions shown in gray assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data
Input Set Up Time.
X
X
CW
First Write
Burst Write
W
Simplified State Diagram with G
W
CW
10/21
W
CR
R
CR
R
Deselect
X
CW
W
CW
W
R
CR
First Read
Burst Read
R
R
GS820E32AT-180/166/133/4/5
CR
X
X
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