OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 115

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Special Function Blocks Timing
Table 49. Microprocessor Interface (MP I) Timing Characteristics
OR3Cxx Commercial: V
OR3Txxx Commercial: V
1. For user system flexibility,
2. 0.5 MPI_CLK.
3. Write data and W/R have to be valid starting from the clock cycle after both ADS and CS0 and CS1 are recognized.
4. Write data and W/R have to be held until the microprocessor receives a valid RDYRCV.
Notes:
Read and write descriptions are referenced to the host microprocessor; e.g., a read is a read by the host ( PowerPC , i960 ) from the FPGA.
PowerPC and i960 timings to/from the clock are relative to the clock at the FPGA microprocessor interface clock pin (MPI_CLK).
PowerPC Interface Timing (T
Transfer Acknowledge Delay (CLK to TA)
Burst Inhibit Delay (CLK to BIN)
Transfer Acknowledge Delay to High Impedance
Burst Inhibit Delay to High Impedance
Write Data Setup Time (data to TS)
Write Data Hold Time (data from CLK while MPI_ACK low)
Address Setup Time (addr to TS)
Address Hold Time (addr from CLK while MPI_ACK low)
Read/Write Setup Time (R/W to TS)
Read/Write Hold Time (R/W from CLK while MPI_ACK low)
Chip Select Setup Time (CS0, CS1 to TS)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (pad to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
i960 Interface Timing (T
Addr/Data Select to ALE (ADS, to ALE low)
Addr/Data Select to ALE (ADS, from ALE low)
Ready/Receive Delay (CLK to RDYRCV)
Ready/Receive Delay to High Impedance
Write Data Setup Time
Write Data Hold Time
Address Setup Time (addr to ALE low)
Address Hold Time (addr from ALE low)
Byte Enable Setup Time (BE0, BE1 to ALE low)
Byte Enable Hold Time (BE0, BE1 from ALE low)
Read/Write Setup Time
Read/Write Hold Time
Chip Select Setup Time (CS0, CS1 to CLK)
Chip Select Hold Time (CS0, CS1 from CLK)
User Address Delay (CLK low to UA[3:0])
User Read/Write Delay (pad to URDWR_DEL)
MPI_STRB
inactive before the end of the read/write cycle.
is low. If both chip selects are valid and the setup time is met, the MPI will latch the chip select state, and
DD
DD
Parameter
J
CS0
= 5.0 V ± 5%, 0 °C
= 85 °C, V
= 3.0 V to 3.6 V, 0 °C
and CS1 may be set up to any one of the three rising clock edges, beginning with the rising clock edge when
J
= 85 °C, V
(continued)
DD
= min)
DD
(1)
(1)
<
= min)
T
<
A
<
T
A
70 °C; Industrial: V
<
70 °C; Industrial: V
RDYRCV_DELZ
RDYRCV_DEL
URDWR_DEL
URDWR_DEL
ADSN_SET
ADSN_HLD
TA_DELZ
WD_HLD
RW_HLD
WD_HLD
RW_HLD
BI_DELZ
WD_SET
RW_SET
WD_SET
RW_SET
CS_HLD
CS_HLD
CS_SET
UA_DEL
BE_SET
BE_HLD
CS_SET
UA_DEL
TA_DEL
Symbol
BI_DEL
A_HLD
A_HLD
A_SET
A_SET
DD
DD
= 5.0 V ± 10%, –40 °C
= 3.0 V to 3.6 V, –40 °C
Min Max Min Max Min Max Min Max
0.0
0.0
0.0
0.0
0.0
0.0
0.3
0.0
2.0
0.0
2.0
2.0
2.0
2.0
2.0
0.0
—
—
—
—
—
—
—
—
(3)
(4)
(3)
(4)
—
—
ORCA Series 3C and 3T FPGAs
–4
11.6
11.6
11.6
3.3
7.0
6.6
7.0
(2)
(2)
—
—
—
—
—
—
—
—
—
—
(2)
—
—
—
—
—
—
—
—
—
—
0.0
0.0
0.0
0.0
0.0
0.0
.25
0.0
1.8
0.0
1.8
1.8
1.8
1.8
1.8
0.0
—
—
—
—
—
—
—
—
(3)
(4)
(3)
(4)
—
—
–5
9.3
9.3
2.6
5.4
9.3
4.3
5.4
(2)
(2)
—
—
—
—
—
—
—
—
—
—
(2)
—
—
—
—
—
—
—
—
—
—
Speed
<
T
A
0.50
0.51
0.50
0.51
0.45
0.0
0.0
0.0
0.0
0.0
0.0
.14
0.0
1.6
0.0
0.0
<
—
—
—
—
—
—
—
—
(3)
(4)
(3)
(4)
—
—
<
CS0
T
–6
+85 °C.
A
and CS1 may go
<
8.0
8.0
2.3
4.2
8.0
4.1
4.2
(2)
(2)
—
—
—
—
—
—
—
—
—
—
(2)
—
—
—
—
—
—
—
—
—
—
+85 °C.
0.0
0.0
0.0
0.0
0.0
0.0
.12
0.0
1.4
0.0
0.0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)
(4)
(3)
(4)
–7
0.42
0.44
0.42
0.44
0.38
6.8
6.8
1.9
3.6
6.8
3.5
3.6
115
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(2)
(2)
(2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns