OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 43

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Programmable Input/Output Cells
(continued)
PIO Logic Function Generator
The PIO logic block can also generate logic functions
based on the signals on the OUT2 and CLK ports of
the PIO. The functions are AND, NAND, OR, NOR,
XOR, and XNOR. Table 10 is provided as a summary
of the PIO logic options.
Table 10. PIO Logic Options
Lucent Technologies Inc.
OUT1OUTREG
OUT2OUTREG
OUT1OUT2
Option
XNOR
NAND
NOR
XOR
AND
OR
Data at OUT1 output when clock
low, data at FF out when clock
high.
Data at OUT2 output when clock
low, data at FF out when clock
high.
Data at OUT1 output when clock
low, data at OUT2 when clock
high.
Output logical AND of signals on
OUT2 and clock.
Output logical NAND of signals
on OUT2 and clock.
Output logical OR of signals on
OUT2 and clock.
Output logical NOR of signals on
OUT2 and clock.
Output logical XOR of signals on
OUT2 and clock.
Output logical XNOR of signals
on OUT2 and clock.
Description
PIO Register Control Signals
As discussed in the Inputs and Outputs subsections,
the PIO latches/FFs have various clock, clock enable
(CE), local set/reset (LSR), and global set/reset
(GSRN) controls. Table 11 provides a summary of
these control signals and their effect on the PIO
latches/FFs. Note that all control signals are optionally
invertible.
Table 11. PIO Register Control Signals
Global Set/Reset
Set/Reset Mode The input latch/FF, output FF, and
Local Set/Reset
Control Signal
System Clock
Clock Enable
ExpressCLK
(GSRN)
(SCLK)
(LSR)
(CE)
ORCA Series 3C and 3T FPGAs
Clocks input fast-capture latch;
optionally clocks output FF, or
3-state FF.
Clocks input latch/FF; optionally
clocks output FF, or 3-state FF.
Optionally enables/disables input
FF (not available for input latch
mode); optionally enables/dis-
ables output FF; separate CE
inversion capability for input and
output.
Option to disable; affects input
latch/FF, output FF, and 3-state
FF if enabled.
Option to enable or disable per
PIO after initial configuration.
3-state FF are individually set or
reset by both the LSR and GSRN
inputs.
Effect/Functionality
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