OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 150

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Pin Information
Table 67. Pin Descriptions (continued)
150
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
Special-Purpose Pins (continued)
RDY/RCLK/
TDI, TCK,
MPI_ALE
Symbol
TMS
HDC
LDC
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
INIT
M3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
During powerup and initialization, M3 is used to select the speed of the internal oscillator dur-
ing configuration with their values latched on the rising edge of
oscillator frequency is 10 MHz. When M3 is high, the oscillator is 1.25 MHz. During configura-
tion, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
If boundary scan is used, these pins are test data in, test clock, and test mode select inputs. If
boundary scan is not selected, all boundary-scan functions are inhibited once configuration is
complete. Even if boundary scan is not used, either TCK or TMS must be held at logic 1 dur-
ing configuration. Each pin has a pull-up enabled during configuration.
After configuration, these pins are user-programmable I/O (see Note).
During configuration in peripheral mode, RDY/RCLK indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is also
available on D7 in asynchronous peripheral mode.
During the master parallel configuration mode, RCLK is a read output signal to an external
memory. This output is not normally used.
In i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
High During Configuration is output high until configuration is complete. It is used as a control
output, indicating that configuration is not complete.
After configuration, this pin is a user-programmable I/O pin (see Note).
Low During Configuration
put, indicating that configuration is not complete.
After configuration, this pin is a user-programmable I/O pin (see Note).
INIT
enabled, but an external pull-up resistor is recommended. As an active-low open-drain out-
put,
low input,
After configuration, this pin is a user-programmable I/O pin (see Note).
(continued)
is a bidirectional signal before and during configuration. During configuration, a pull-up is
INIT
is held low during power stabilization and internal clearing of memory. As an active-
INIT
holds the FPGA in the wait-state before the start of configuration.
is output low until configuration is complete. It is used as a control out-
Description
INIT
. When M3 is low, the
Lucent Technologies Inc.
Data Sheet
June 1999