OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 207

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Index
Absolute Maximum Ratings, 96
AND-OR-INVERT (AOI), 6
AND-OR-INVERT (AOI),1
Architecture
ASWE, 9, 11, 15—17, 23, 33, 48
Bidirectional Buffers (BIDIs), 6, 19, 43, 83
Bit Stream (see FPGA Configuration)
Bit Stream Error Checking, 88
Boundary Scan, 55
Clock Control (CLKCNTRL), 50
Clock Distribution Network, 48–51
Clock Enable (CE), 9, 11, 17, 23, 31, 48
Clock Multiplication (see PCM)
Comparator (see LUT Operating Modes)
Configuration (see FPGA States of Operation
Control Inputs (see PICs, Inputs)
Demultiplexing (see PICs, Input Demultiplexing), 38
Duty-Cycle Adjustment (see PCM)
Lucent Technologies Inc.
Overview, 6—9
CLKCNTRL, 50
ExpressCLK, 48
Fast Clock, 48, 51
Global Control Signals, 48
In the PICs
In the PLC Array
PFU Clock Sources, 48
Selecting Clock Input Pins, 51
System Clock, 48
To the PLC Array
(see also Supplemental Logic
Interconnect Cell (SLIC), 1
(see also Routingand SLIC)
(see also FPGA states of Operation)
(see Special Function Blocks)
(see also Clock Distribution Network and
Special Function Blocks)
Inputs, 51
ExpressCLK, 50
System Clock, 50
Fast Clock, 49
System Clock, 49
Fast Clock, 50
System Clock, 50
or FPGA Configuration)
A
B
C
D
Electrical Characteristics, 97, 98
Error Checking (see FPGA Configuration)
ExpressCLK, 1, 6, 31, 34, 37, 39, 41, 43, 47—51,
Fast Clock, 46—51, 54
5 V Tolerant I/O 35
Flexible Input Structure (FINS) 1, 27, 32
FPGA Configuration, 87—94
FPGA States of Operation
IEEE Standard, 1149.1 55, 59
Initialization (see FPGA States of Operation)
Input/Output Buffers
JTAG (see Boundry Scan)
Configuration Frame Format, 87
Configuration Modes, 89
Data Format, 86
Data Frame, 86
Using ORCA Foundry to Generate RAM Data, 86
Configuration, 83
Initialization, 82
Other Configuration Options, 85
Partial Reconfiguration, 85
Reconfiguration, 85
Start-Up, 84
Measurement Conditions, 138
Output Buffer Characteristics
70—74, 77—81
(see also Clock distribution Network and
Programmable Clock Manager)
(see Clock Distribution Network)
(see also Routing)
Asynchronous Peripheral Mode, 91
Daisy-Chaining, 95
Master Parallel Mode, 89
Master Serial Mode, 90
Microprocessor Interface (MPI) Mode, 91
Slave Parallel Mode, 94
Slave Serial Mode, 94
OR3Cxx, 139
OR3Txxx, 141
ORCA Series 3C and 3T FPGAs
E
F
J
I
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