OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 54

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Special Function Blocks
Special function blocks in the Series 3 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners and MIDs (middle inter-
quad areas) of the FPGA array.
Single Function Blocks
Most of the special function blocks perform a specific
dedicated function. These functions are data/configura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA and can be enabled via a bit stream option
or by instantiation of a library readback component.
Readback is used to read back the configuration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the ORCA
Foundry Development System.
Table 12 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the configuration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s configuration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Table 12. Readback Options
54
54
Option
U
0
1
Prohibit Readback
Allow One Readback Only
Allow Unrestricted Number of Readbacks
Function
Readback can be performed via the Series 3 micropro-
cessor interface ( MPI ) or by using dedicated FPGA
readback controls. If the MPI is enabled, readback via
the dedicated FPGA readback logic is disabled. Read-
back using the MPI is discussed in the Microprocessor
Interface ( MPI ) section.
The pins used for dedicated readback are readback
data (RD_DATA), read configuration (
configuration clock (CCLK). A readback operation is ini-
tiated by a high-to-low transition on
RD_CFG
operation. The readback operation can be restarted at
frame 0 by driving the
least two rising edges of CCLK, and then driving
RD_CFG
RD_DATA at the rising edge of CCLK. The first start bit
of the readback frame is transmitted out several cycles
after the first rising edge of CCLK after
low (see the Readback Timing Characteristics table in
the Timing Characteristics section). To be certain of the
start of the readback frame, the data can be monitored
for the 01 frame start bit pair.
Readback can be initiated at an address other than
frame 0 via the new microprocessor interface ( MPI )
control registers (see the Microprocessor Interface
( MPI ) section for more information). In all cases, read-
back is performed at sequential addresses from the
start address.
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The
the global 3-state (TS_ALL) function. Before and during
configuration, the TS_ALL signal is always driven by
the
figuration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
RD_CFG
input must remain low during the readback
low again. One bit of data is shifted out on
input and readback is disabled. After con-
RD_CFG
input pin is also used to control
RD_CFG
Lucent Technologies Inc.
pin high, applying at
RD_CFG
RD_CFG
RD_CFG
Data Sheet
June 1999
. The
RD_CFG
), and
is input