OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 152

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

ORCA Series 3C and 3T FPGAs
Pin Information
Table 67. Pin Descriptions (continued)
152
Note: The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
Special-Purpose Pins (continued)
A7/MPI_CLK
A11/
A8/MPI_RW
A9/
A10/
MPI_BE[1:0]
Symbol
A[1:0]/
DOUT
A[4:0]
D[7:0]
MPI_ACK
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the
activation of all user I/Os) is controlled by a second set of options.
DIN
MPI_IRQ
MPI_BI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
I
I
I
I
I
I
MPI active-low interrupt request output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
PowerPC mode MPI burst inhibit output.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
In PowerPC mode MPI operation, this is the active-high transfer acknowledge (
i960 MPI operation, it is the active-low ready/record (
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
In PowerPC mode MPI operation, this is the active-low write/active-high read control signals.
For i960 operation, it is the active-high write/active-low read control signal.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
This is the clock used for the synchronous MPI interface. For PowerPC , it is the CLKOUT
signal. For i960 , it is the system clock that is chosen for the i960 external bus interface.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
For PowerPC operation, these are the PowerPC address inputs. The address bit mapping (in
PowerPC /FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/A[3], A[27]/A[4]. Note
that A[27]/A[4] is the MSB of the address. The A[4:2] inputs are not used in i960 MPI mode.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
For i960 operation,
address bits A[1:0] in i960 byte-wide operation.
After configuration, if the MPI is not used, this pin is a user-programmable I/O pin (see Note).
During master parallel, peripheral, and slave parallel configuration modes, D[7:0] receive
configuration data, and each pin has a pull-up enabled. During serial configuration modes, D0
is the DIN input. D[7:0] are also the data pins for PowerPC microprocessor mode and the
address/data pins for i960 microprocessor mode.
After configuration, the pins are user-programmable I/O pins (see Note).
During slave serial or master serial configuration modes, DIN accepts serial configuration
data synchronous with CCLK. During parallel configuration modes, DIN is the D0 input. Dur-
ing configuration, a pull-up is enabled.
After configuration, this pin is a user-programmable I/O pin (see Note).
During configuration, DOUT is the serial data output that can drive the DIN of daisy-chained
slave LCA devices. Data out on DOUT changes on the falling edge of CCLK.
After configuration, DOUT is a user-programmable I/O pin (see Note).
(continued)
MPI_BE[1:0]
provide the i960 byte enable signals,
Description
RDYRCV
) output.
Lucent Technologies Inc.
BE[1:0]
, that are used as
TA
Data Sheet
) output. For
June 1999