OR3T125-5BA352 AGERE [Agere Systems], OR3T125-5BA352 Datasheet - Page 127

• Manufacturer Part Number: OR3T125-5BA352
• Description: 3C and 3T Field-Programmable Gate Arrays
• Manufacturer: AGERE [Agere Systems]

Data Sheet
June 1999
Lucent Technologies Inc.
Timing Characteristics
Table 56 . OR3Cxx General System Clock (SCLK) to Output Delay (Pin-to-Pin)
OR3Cxx Commercial: V
OR3Txxx Commercial: V
C
Note:
This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay, the clock routing to the
PIO CLK input, the clock Q of the FF, and the delay through the output buffer. The delay will be reduced if any of the clock branches are not
used. The given timing requires that the input clock pin be located at one of the four center PICs on any side of the device and that a PIO FF be
used. For clock pins located at any other PIO, see the results reported by ORCA Foundry.
Output On Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Clock Input Pin (mid-PIC)
Clock Input Pin (mid-PIC)
Clock Input Pin (mid-PIC)
Additional Delay if Non-mid-PIC Used as Clock
Output Not on Same Side of Device As Input Clock (System Clock Delays Using General User I/O Inputs)
Additional Delay if Output Not on Same Side as
L =
(Slewlim)
(Sinklim)
Pin
Input Clock Pin
50 pF.
(T
J
= 85 °C, V
Description
DD
DD
DD
= 5.0 V ± 5%, 0 °C
= 3.0 V to 3.6 V, 0 °C
OUTPUT Pin (Fast)
OUTPUT Pin
OUTPUT Pin
= min)
SCLK
(continued)
Figure 78. System Clock to Output Delay
<
T
A
<
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3C/T55
OR3C/T80
OR3T125
OR3T125
OR3T125
OR3T125
OR3T125
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
OR3T20
OR3T30
<
Device
T
D
A
70 °C; Industrial: V
PIO FF
<
70 °C; Industrial: V
Q
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-4
OUTPUT (50 pF LOAD)
14.91
15.71
17.34
18.14
18.70
19.51
Max
0.41
0.63
0.41
0.63
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DD
= 5.0 V ± 10%, –40 °C
DD
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
= 3.0 V to 3.6 V, –40 °C
ORCA Series 3C and 3T FPGAs
-5
12.17
12.80
13.69
13.34
13.62
14.16
14.79
15.68
14.69
14.97
15.51
16.14
17.03
11.35
11.63
Max
0.16
0.20
0.36
0.55
0.16
0.20
0.36
0.55
1.11
1.11
Speed
Min
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-6
<
13.26
13.45
13.80
14.18
14.76
Max
7.74
7.93
8.28
8.66
9.24
8.42
8.60
8.95
9.34
9.91
0.18
0.21
0.37
0.57
1.05
0.18
0.21
0.37
0.57
1.05
T
A
<
<
+85 °C; C
T
Min
A
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
<
-7
+85 °C;
12.22
12.76
11.37
11.54
11.86
Max
6.10
6.27
6.59
6.95
7.49
6.63
6.80
7.12
7.48
8.02
0.17
0.20
0.35
0.55
1.02
0.17
0.20
0.35
0.55
1.02
L
= 50 pF.
5-4846(F)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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