EN29F002AB-45JC EON [Eon Silicon Solution Inc.], EN29F002AB-45JC Datasheet - Page 13

• Manufacturer Part Number: EN29F002AB-45JC
• Description: 2 Megabit (256K x 8-bit) Flash Memory
• Manufacturer: EON [Eon Silicon Solution Inc.]

DATA PROTECTION
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even
with CE = V
Low V
During V
unintentional writes. If V
erase circuits are disabled. Under this condition, the device will reset to the READ mode.
Subsequent writes will be ignored until V
Write “Noise” Pulse Protection
Noise pulses less than 5ns on OE , CE or WE will neither initiate a write cycle nor change the
command register.
Logical Inhibit
If CE =V
“zero”. If CE ,
write.
Sector Protection/Unprotection
When the device is shipped, all sectors are unprotected. Each sector can be separately protected
against data changes. Using hardware protection circuitry enabled at user’s site with external
programming equipment, both program and erase operations may be disabled for any specified
sector or combination of sectors.
Verification of write protection for a specific sector can be achieved with an Auto Select ID read
command at location 02h where the address bits A17 - A13 select the defined sector (see Table 5).
A logical “1” at DQ0 means a protected sector and a logical “0” means an unprotected sector.
The Sector Unprotect disables sector protection in all sectors in one operation to implement code
changes. All sectors must be placed in protection mode using the protection algorithm mentioned
above before unprotection can be executed.
Additional details on this feature are provided in a supplement, which can be obtained by contacting
a representative of Eon Silicon Solution, Inc.
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
W E
.
CC
IH
CC
or
Write Inhibit
power-up or power-down
IL
WE
, W E = V
W E
=V
, and OE are all logical zero (not recommended usage), it will be considered a
IH
, writing is inhibited. To initiate a write cycle, CE and
IL
CC
and OE = V
< V
LKO
, the command register is disabled and all internal program or
,
the EN29F002A locks out write cycles to protect against any
IH
, the device will not accept commands on the rising edge of
CC
> V
LKO.
Rev. A, Issue Date: 2003/03/26
13
©2003 Eon Silicon Solution, Inc., www.essi.com.tw
EN29F002A / EN29F002AN
W E
must be a logical