EMC326SP16AK Emlsi Inc., EMC326SP16AK Datasheet - Page 15

• Manufacturer Part Number: EMC326SP16AK
• Description: 2mx16 Bit Cellularram
• Manufacturer: Emlsi Inc.

Mixed-Mode Operation
The device supports a combination of synchronous READ and asynchronous READ and WRITE operations when the BCR is
configured for synchronous operation. (Some vendors also support asychronous READ.) The asynchronous READ and WRITE
operations require that the clock (CLK) remain LOW during the entire sequence. The ADV# signal can be used to latch the target
address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between mixed-mode
operations with fixed latency enabled; however, the CE# LOW time must not exceed t
seamless interface to legacy burst mode Flash memory controllers. See Figure 47 for the “Asychronous WRITE Followed by Burst
READ”timing diagram.
WAIT Operation
The WAIT output on a CellularRAM device is typically connected to a shared, system-level WAIT signal. (See Figure 9.) The shared
WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus.
Figure 9: Wired or WAIT Configuration
When a READ or WRITE operation has been initiated, WAIT goes active to indicate that the CellularRAM device requires additional
time before data can be transferred. For READ operations, WAIT will remain active until valid data is output from the device. For
WRITE operations, WAIT will indicate to the memory controller when data will be accepted into the CellularRAM device. When WAIT
transitions to an inactive state, the data burst will progress on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during WAIT cycles may cause data
corruption. When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for READ operations
launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock cycles until the refresh has
completed. (See Figure 8) When the refresh operation has completed, the READ operation will continue normally.
WAIT will be asserted but should be ignored during asynchronous READ and WRITE, and page READ operations. By using fixed
initial latency (BCR[14] = 1), this CellularRAM device can be used in burst mode without monitoring the WAIT signal. However, WAIT
can still be used to determine when valid data is available at the start of the burst and at the end of row. If WAIT is not monitored, the
controller must stop burst accesses at row boundaries on its own.
LB#/UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled bytes will not be
transferred to the RAM array and the internal value will remain unchanged. During an asynchronous WRITE cycle, the data to be
written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first. LB# and UB# must be LOW during READ
cycles. When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from receiving or
transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as CE# remains LOW.
Processor
READY
CellularRAM
Other
Device
WAIT
WAIT
Other
Device
WAIT
15
External
Pull-Up/
Pull-Down
Resistor
CEM
. Mixed-mode operation facilitates a
EMC326SP16AK
2Mx16 CellularRAM