ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 163

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Serial
Peripheral
Interface – SPI
2467S–AVR–07/09
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega128 and peripheral devices or between several AVR devices. The ATmega128 SPI
includes the following features:
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Figure 75. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
tem consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective Shift Registers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Mas-
ter to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
/2/4/8/16/32/64/128
Refer to
DIVIDER
Figure 1 on page 2
and
Table 30 on page 74
for SPI pin placement.
ATmega128
Figure
76. The sys-
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