ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 67

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Ports as General
Digital I/O
Configuring the Pin
2467S–AVR–07/09
The ports are bi-directional I/O ports with optional internal pull-ups.
description of one I/O port pin, here generically called Pxn.
Figure 30. General Digital I/O
Note:
Each port pin consists of three Register bits: DDxn, PORTxn, and PINxn. As shown in
Description for I/O Ports” on page
PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when a Reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled ({DDxn, PORTxn} = 0b01) or output
Pxn
1. WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk
and PUD are common to all ports.
PUD:
SLEEP:
clk
I/O
:
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
(1)
87, the DDxn bits are accessed at the DDRx I/O address, the
SLEEP
SYNCHRONIZER
WDx:
RDx:
WPx:
RRx:
RPx:
D
L
Q
Q
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
PINxn
Q
Q
Figure 30
RESET
RESET
PORTxn
Q
Q
Q
Q
DDxn
CLR
CLR
D
D
ATmega128
shows a functional
PUD
WDx
RDx
WPx
RPx
clk
RRx
I/O
I/O
“Register
, SLEEP,
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