ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 29

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Pull-up and Bus-
keeper
Timing
2467S–AVR–07/09
The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to
one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by
writing the Port register to zero before entering sleep.
The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be dis-
abled and enabled in software as described in
on page
AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.
External Memory devices have different timing requirements. To meet these requirements, the
ATmega128 XMEM interface provides four different wait-states as shown in
tant to consider the timing specification of the External Memory device before selecting the wait-
state. The most important parameters are the access time for the external memory compared to
the set-up requirement of the ATmega128. The access time for the External Memory is defined
to be the time from receiving the chip select/address until the data of this address actually is
driven on the bus. The access time cannot exceed the time from the ALE pulse must be
asserted low until data is stable during a read sequence (See t
through Tables 144 on pages 328 - 330). The different wait-states are set up in software. As an
additional feature, it is possible to divide the external memory space in two sectors with individ-
ual wait-state settings. This makes it possible to connect two different memory devices with
different timing requirements to the same XMEM interface. For XMEM interface timing details,
please refer to
ory Timing” on page
Note that the XMEM interface is asynchronous and that the waveforms in the following figures
are related to the internal system clock. The skew between the internal and external clock
(XTAL1) is not guarantied (varies between devices temperature, and supply voltage). Conse-
quently, the XMEM interface is not suited for synchronous operation.
Figure 13. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)
Note:
System Clock (CLK
1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or
33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the
DA7:0 (XMBK = 0)
DA7:0 (XMBK = 1)
SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction
accesses the RAM (internal or external).
Table 137
DA7:0
A15:8
CPU
ALE
WR
RD
328.
)
Prev. addr.
Prev. data
Prev. data
Prev. data
to
Table 144
T1
and
Address
Figure 157
Address
Address
“External Memory Control Register B – XMCRB”
T2
XX
XXXXX
to
Figure 160
Address
T3
Data
Data
Data
LLRL
+ t
in the
RLRH
ATmega128
XXXXXXXX
- t
“External Data Mem-
T4
Table
DVRH
in Tables 137
4. It is impor-
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