ATMEGA128-16AU SL383 Atmel, ATMEGA128-16AU SL383 Datasheet - Page 225

• Manufacturer Part Number: ATMEGA128-16AU SL383
• Manufacturer: Atmel

Table 92. Miscellaneous States
Combining Several
TWI Modes
Multi-master
Systems and
Arbitration
2467S–AVR–07/09
Status Code
(TWSR)
Prescaler Bits
are 0
$F8
$00
Status of the Two-wire Serial
Bus and Two-wire Serial Inter-
face Hardware
No relevant state information
available; TWINT = “0”
Bus error due to an illegal
START or STOP condition
Status $F8 indicates that no relevant information is available because the TWINT flag is not set.
This occurs between other states, and when the TWI is not involved in a serial transfer.
Status $00 indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed slave mode and to clear the TWSTO flag (no other bits in TWCR
are affected). The SDA and SCL lines are released, and no STOP condition is transmitted.
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated
2. The EEPROM must be instructed what location should be read
3. The reading must be performed
4. The transfer must be finished
Note that data is transmitted both from master to slave and vice versa. The master must instruct
the slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multimaster sys-
tem, another master can alter the data pointer in the EEPROM between steps 2 and 3, and the
master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 104. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
S
S = START
Application Software Response
To/from TWDR
No TWDR action
No TWDR action
Transmitted from master to slave
SLA+W
A
To TWCR
STA
No TWCR action
0
Master Transmitter
ADDRESS
STO
1
TWINT
1
A
Rs = REPEATED START
Rs
Transmitted from slave to master
TWEA
X
SLA+R
Wait or proceed current transfer
Only the internal hardware is affected, no STOP condi-
tion is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
Next Action Taken by TWI Hardware
A
Master Receiver
ATmega128
DATA
P = STOP
A
P
225