ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 123

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Serial Downloading
Serial Programming Pin
Mapping
1477J–AVR–06/07
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI
bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI
(input) and MISO (output). After RESET is set low, the Programming Enable instruction
needs to be executed first before program/erase operations can be executed. NOTE, in
Table 59 on page 123, the pin mapping for SPI programming is listed. Not all parts use
the SPI pins dedicated for the internal SPI interface. Note that throughout the descrip-
tion about Serial downloading, MOSI and MISO are used to describe the serial data in
and serial data out respectively.
Table 59. Pin Mapping Serial Programming
Figure 67. Serial Programming and Verify
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed pro-
gramming operation (in the serial mode ONLY) and there is no need to first execute the
Chip Erase instruction. The Chip Erase operation turns the content of every memory
location in both the Program and EEPROM arrays into $FF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high
periods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
1. If the device is clocked by the internal oscillator, there is no need to connect a clock
2. V
Symbol
source to the XTAL1 pin.
MOSI
MISO
SCK
CC
-0.3V < AVCC < V
MOSI
MISO
SCK
CC
ck
ck
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
Pins
+0.3V, however, AVCC should always be within 2.7 - 5.5V.
PB0
PB1
PB2
PB0
PB1
PB2
XTAL1
RESET
GND
(1)
I/O
O
I
I
AVCC
VCC
Description
Serial data in
Serial data out
Serial clock
2.7 - 5.5V
2.7 - 5.5V
ATtiny26(L)
(2)
ck
ck
≥ 12 MHz
≥ 12 MHz
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