ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 61

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

General Interrupt Flag
Register – GIFR
Timer/Counter Interrupt Mask
Register – TIMSK
1477J–AVR–06/07
interrupt is activated on rising or falling edge, on pin change, or low level of the INT0 pin.
Activity on the pin will cause an interrupt request even if INT0 is configured as an output.
The corresponding interrupt of External Interrupt Request 0 is executed from program
memory address $001. See also “External Interrupt” on page 64.
• Bit 5 – PCIE1: Pin Change Interrupt Enable1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the interrupt pin change is enabled on analog pins PB[7:4], PA[7:6] and PA[3]. Unless
the alternate function masks out the interrupt, any change on the pin mentioned before
will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is
executed from program memory address $002. See also “Pin Change Interrupt” on
page 64.
• Bit 4– PCIE0: Pin Change Interrupt Enable0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the interrupt pin change is enabled on digital pins PB[3:0]. Unless the alternate function
masks out the interrupt, any change on the pin mentioned before will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from program
memory address $002. See also “Pin Change Interrupt” on page 64.
• Bits 3..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the ATtiny26(L) and always reads as zero.
• Bit 6 – INTF0: External Interrupt Flag0
When an event on the INT0 pin triggers an interrupt request, INTF0 becomes set (one).
If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the
Interrupt Vector at address $001. The flag is cleared when the interrupt routine is exe-
cuted. Alternatively, the flag can be cleared by writing a logical one to it. The flag is
always cleared when INT0 is configured as level interrupt.
• Bit 5 – PCIF: Pin Change Interrupt Flag
When an event on pins PB[7:0], PA[7:6], or PA[3] triggers an interrupt request, PCIF
becomes set (one). PCIE1 enables interrupt from analog pins PB[7:4], PA[7:6], and
PA[3]. PCIE0 enables interrupt on digital pins PB[3:0]. Note that pin change interrupt
enable bits PCIE1 and PCIE0 also mask the flag if they are not set. For example, if
PCIE0 is cleared, a pin change on PB[3:0] does not set PCIF. If an alternate function is
enabled on a pin, PCIF is masked from that individual pin. If the I-bit in SREG and the
PCIE bit in GIMSK are set (one), the MCU will jump to the Interrupt Vector at address
$002. The flag is cleared when the interrupt routine is executed. Alternatively, the flag
can be cleared by writing a logical one to it. See also “Pin Change Interrupt” on page 64.
• Bits 4..0 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit
$3A ($5A)
Read/Write
Initial Value
Bit
$39 ($59)
7
–
R
7
–
0
OCIE1A
INTF0
R/W
6
0
6
OCIE1B
PCIF
R/W
5
0
5
R
4
–
0
4
–
3
–
R
0
3
–
R
2
–
0
TOIE1
2
ATtiny26(L)
R
1
–
0
TOIE0
1
R
0
–
0
0
–
GIFR
TIMSK
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