ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 85

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

1477J–AVR–06/07
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the
outputs are affected by these bits. Data and clock inputs are not affected by the mode
selected and will always have the same function. The counter and Shift Register can
therefore be clocked externally, and data input sampled, even when outputs are
disabled. The relations between USIWM1..0 and the USI operation is summarized in
Table 39.
When Two-wire mode is selected, the USISIF flag is set (to one) when a start condition
is detected. When output disable mode or Three-wire mode is selected and (USICSx =
0b11 & USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets
the flag.
Table 39. Relations between USIWM1..0 and the USI Operation
Note:
USIWM1
0
0
1
1
1. The DI and SCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL)
respectively to avoid confusion between the modes of operation.
USIWM0
0
1
0
1
Outputs, clock hold, and start detector disabled. Port pins operates as
normal.
Three-wire mode. Uses DO, DI, and SCK pins.
The Data Output (DO) pin overrides the PORTB1 bit in the PORTB
Register in this mode. However, the corresponding DDRB1 bit still
controls the data direction. When the port pin is set as input
(DDRB1 = 0) the pins pull-up is controlled by the PORTB1 bit.
The Data Input (DI) and Serial Clock (SCK) pins do not affect the
normal port operation. When operating as master, clock pulses are
software generated by toggling the PORTB2 bit while DDRB2 is set to
output. The USITC bit in the USICR Register can be used for this
purpose.
Two-wire mode. Uses SDA (DI) and SCL (SCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-
directional and uses open-collector output drives. The output drivers
are enabled by the DDRB0/2 bit in the DDRB Register.
When the output driver is enabled for the SDA pin, the output driver will
force the line SDA low if the output of the Shift Register or the PORTB0
bit in the PORTB Register is zero. Otherwise the SDA line will not be
driven (i.e., it is released). When the SCL pin output driver is enabled
the SCL line will be forced low if the PORTB2 bit in the PORTB
Register is zero, or by the start detector. Otherwise the SCL line will
not be driven.
The SCL line is held low when a start detector detects a start condition
and the output is enabled. Clearing the start condition flag (USISIF)
releases the line. The SDA and SCL pin inputs is not affected by
enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except
that the SCL line is also held low when a counter overflow occurs, and
is held low until the Counter Overflow Flag (USIOIF) is cleared.
Description
ATtiny26(L)
(1)
.
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