ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 74

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Timer/Counter1 – TCNT1
Timer/Counter1 Output
Compare RegisterA – OCR1A
74
ATtiny26(L)
• Bits 3..0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0
The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.
Table 34. Timer/Counter1 Prescale Select
The Stop condition provides a Timer Enable/Disable function.
This 8-bit register contains the value of Timer/Counter1.
Timer/Counter1 is realized as an up counter with read and write access. Due to syn-
chronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by
one CPU clock cycle in synchronous mode and at most two CPU clock cycles for asyn-
chronous mode.
The Output Compare Register A is an 8-bit read/write register.
The Timer/Counter Output Compare Register A contains data to be continuously com-
pared with Timer/Counter1. Actions on compare matches are specified in TCCR1A. A
compare match does only occur if Timer/Counter1 counts to the OCR1A value. A soft-
Bit
$2E ($4E)
Read/Write
Initial Value
Bit
$2D ($4D)
Read/Write
Initial Value
CS13
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CS12
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MSB
MSB
R/W
R/W
7
0
7
0
CS11
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R/W
R/W
6
0
6
0
CS10
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R/W
R/W
5
0
5
0
Description
Asynchronous Mode
Timer/Counter1 is stopped.
PCK
PCK/2
PCK/4
PCK/8
PCK/16
PCK/32
PCK/64
PCK/128
PCK/256
PCK/512
PCK/1024
PCK/2048
PCK/4096
PCK/8192
PCK/16384
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
R/W
R/W
2
0
2
0
Description
Synchronous Mode
Timer/Counter1 is stopped.
CK
CK/2
CK/4
CK/8
CK/16
CK/32
CK/64
CK/128
CK/256
CK/512
CK/1024
CK/2048
CK/4096
CK/8192
CK/16384
R/W
R/W
1
0
1
0
LSB
R/W
LSB
R/W
0
0
0
0
1477J–AVR–06/07
OCR1A
TCNT1