ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 19

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

EEPROM Data Memory
EEPROM Read/Write Access
EEPROM Address Register –
EEAR
1477J–AVR–06/07
The five different addressing modes for the data memory cover: Direct, Indirect with Dis-
placement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In
the Register File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space. The Indirect with Displacement
mode features a 63 address locations reach from the base address given by the Y- or Z-
register.
When using register indirect addressing modes with automatic pre-decrement and post-
increment, the address registers X, Y, and Z are decremented and incremented.
The 32 general purpose working registers, 64 I/O Registers and the 128 bytes of inter-
nal data SRAM in the ATtiny26(L) are all accessible through all these addressing
modes.
See “Program and Data Addressing Modes” on page 12 for a detailed description of the
different addressing modes.
The ATtiny26(L) contains 128 bytes of data EEPROM memory. It is organized as a sep-
arate data space, in which single bytes can be read and written (see “Memory
Programming” on page 109). The EEPROM has an endurance of at least 100,000
write/erase cycles per location.
The EEPROM Access Registers are accessible in the I/O space.
The write access time is typically 8.3 ms. A self-timing function lets the user software
detect when the next byte can be written. A special EEPROM Ready Interrupt can be
set to trigger when the EEPROM is ready to accept new data.
An ongoing EEPROM write operation will complete even if a reset condition occurs.
In order to prevent unintentional EEPROM writes, a two state write procedure must be
followed. Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
When the EEPROM is read, the CPU is halted for four clock cycles before the next
instruction is executed.
• Bit 7 – RES: Reserved Bits
This bit are reserved bit in the ATtiny26(L) and will always read as zero.
• Bit 6..0 – EEAR6..0: EEPROM Address
The EEPROM Address Register – EEAR – specifies the EEPROM address in the 128
bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
127. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Bit
$1E ($3E)
Read/Write
Initial Value
R
7
–
0
EEAR6
R/W
X
6
EEAR5
R/W
5
X
EEAR4
R/W
X
4
EEAR3
R/W
X
3
EEAR2
R/W
2
X
EEAR1
ATtiny26(L)
R/W
1
X
EEAR0
R/W
X
0
EEAR
19