ATTINY26L8SU SL383 Atmel, ATTINY26L8SU SL383 Datasheet - Page 45

• Manufacturer Part Number: ATTINY26L8SU SL383
• Description: MCU 8-Bit ATtiny AVR RISC 2KB Flash 3.3V/5V 20-Pin SOIC T/R
• Manufacturer: Atmel

Reading the Pin Value
1477J–AVR–06/07
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit
in the MCUCR Register can be set to disable all pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The
user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state
({DDxn, PORTxn} = 0b11) as an intermediate step.
Table 21 summarizes the control signals for the pin value.
Table 21. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through
the PINxn Register Bit. As shown in Figure 32, the PINxn Register bit and the preceding
latch constitute a synchronizer. This is needed to avoid metastability if the physical pin
changes value near the edge of the internal clock, but it also introduces a delay. Figure
33 shows a timing diagram of the synchronization when reading an externally applied
pin value. The maximum and minimum propagation delays are denoted t
respectively.
Figure 33. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock.
The latch is closed when the clock is low, and goes transparent when the clock is high,
as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is
latched when the system clock goes low. It is clocked into the PINxn Register at the suc-
ceeding positive clock edge. As indicated by the two arrows t
DDxn
INSTRUCTIONS
0
0
0
1
1
SYSTEM CLK
SYNC LATCH
PORTxn
PINxn
0
1
1
0
1
r17
(in MCUCR)
PUD
X
X
X
0
1
XXX
Output
Output
Input
Input
Input
I/O
t
pd, max
Pull-up
0x00
Yes
No
No
No
No
XXX
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
in r17, PINx
pd,max
ATtiny26(L)
and t
pd,max
pd,min
0xFF
and t
, a single
pd,min
45