MT48LC2M32B2TG-6 :G Micron, MT48LC2M32B2TG-6 :G Datasheet - Page 23
![no-image](/images/no-image-200.jpg)
MT48LC2M32B2TG-6 :G
Manufacturer Part Number
MT48LC2M32B2TG-6 :G
Description
DRAM Chip SDRAM 64M-Bit 3.3V 86-Pin TSOP-II
Manufacturer
Micron
Datasheet
1.MT48LC2M32B2B5-7G.pdf
(69 pages)
- Current page: 23 of 69
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Figure 10:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
Consecutive READ Bursts
Note:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
Each READ command may be to any bank. DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
T0
T0
T0
BANK,
COL n
BANK,
BANK,
READ
COL n
READ
COL n
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
OUT
n
CL = 3
23
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
T3
NOP
NOP
NOP
D
D
n + 2
D
n + 1
OUT
OUT
OUT
n
T4
T4
T4
BANK,
BANK,
BANK,
READ
COL b
READ
COL b
READ
COL b
X = 0 cycles
X = 1 cycle
D
n + 2
D
n + 1
D
n + 3
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
D
n + 2
D
n + 3
OUT
OUT
OUT
b
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
T6
T6
NOP
NOP
D
n + 3
D
OUT
OUT
b
DON’T CARE
Commands
T7
NOP
D
OUT
b
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