IDT74SSTVN16859PAG IDT, Integrated Device Technology Inc, IDT74SSTVN16859PAG Datasheet - Page 3

• Manufacturer Part Number: IDT74SSTVN16859PAG
• Description: IC BUFFER 13-26BIT SSTL 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTVN16859PAG

• Logic Type: 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13, 26
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 2.7ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 220(Min)MHz
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTVN16859PAG

PIN DESCRIPTION
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 -
PC2700
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: T
NOTE:
1. Power dissipation levels will allow operation at DDR333 speeds without excessive die temperature.
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
Center PAD
Symbol
Pin Names
Q
D
RESET
V
I
V
V
I
DDD
C
GND
DD
1
V
V
CLK
1
OH
I
CLK
OL
V
IK
I
DDQ
REF
I
- Q
- D
DD
13
13
Parameter
Control Inputs
All Inputs
Static Standby
Static Operating
Dynamic Operating (Clock Only)
Dynamic Operating
(Per Each Data Input)
Data Inputs
CLK and CLK
RESET
A
= 0°C to +70°C, V
Description
Data Output
Ground
Output-stage drain power voltage
Logic power voltage
Asynchronous reset input - resets registers and disables data and clock differential input recievers
Input reference voltage
Positive master clock input
Negative master clock input
Data Input - clocked in on the crossing of the rising edge of CLK and the falling edge of CLK
Ground (MLF package only)
(1)
DD
= 2.5V ±0.2V, V
Test Conditions
V
V
V
V
V
V
I
I
I
CLK and CLK Switching 50% Duty Cycle.
I
CLK and CLK Switching 50% Duty Cycle. One Data Input
Switching at Half Clock Frequency, 50% Duty Cycle.
V
V
V
O
O
O
O
DD
DD
DD
DD
DD
DD
DD
ICR
I
= 0, V
= 0, V
= 0, V
= 0, V
= V
= 2.3V to 2.7V, I
= 2.3V, I
= 2.3V, I
= 2.3V to 2.7V, I
= 2.3V, I
= 2.7V,VI = V
= 2.5V, V
= 1.25V, V
DD
DD
DD
DD
DD
or GND
= 2.7V, RESET = V
= 2.7V, RESET = V
= 2.7V, RESET = V
= 2.7V, RESET = GND
I
OH
OL
= −18mA
I
DDQ
= V
I (PP)
= 8mA
= -8mA
DD
REF
= 2.5V ±0.2V
OH
OL
= 360mV
or GND
± 310mV
= 100μA
= -100μA
3
DD
DD
DD
, V
, V
, V
I
I
I
= V
= V
= V
IH (AC)
IH (AC)
IH (AC)
or V
or V
or V
IL (AC)
IL (AC)
IL (AC)
,
,
COMMERCIAL TEMPERATURE RANGE
V
DD
Min.
1.95
—
—
—
—
—
—
—
—
2
2
2
– 0.2
Typ.
—
—
—
—
—
—
—
—
43
—
—
—
6
Max.
–1.2
0.35
0.01
0.2
±5
—
—
20
—
—
3
3
3
MHz/Data
μA/Clock
μA/Clock
MHz
Input
Unit
mA
μA
pF
V
V
V