IDT74SSTVN16859PAG IDT, Integrated Device Technology Inc, IDT74SSTVN16859PAG Datasheet - Page 5

• Manufacturer Part Number: IDT74SSTVN16859PAG
• Description: IC BUFFER 13-26BIT SSTL 64-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTVN16859PAG

• Logic Type: 13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs
• Supply Voltage: 2.3 V ~ 2.7 V
• Number Of Bits: 13, 26
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Logic Family: SSTV
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 13
• Number Of Outputs: 26
• High Level Output Current: -16mA
• Low Level Output Current: 16mA
• Propagation Delay Time: 2.7ns
• Operating Supply Voltage (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 220(Min)MHz
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTVN16859PAG

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
NOTES:
1. Data inputs must be low a minimum time of t
2. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
3. For data signal input slew rate is ≥1V/ns.
4.
5. CLK, CLK signal input slew rates are ≥1V/ns.
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
Symbol
CLOCK
t
INACT
t
ACT
t
tw
Symbol
For data signal input slew rate is ≥0.5V/ns and <1V/ns.
SU
t
H
t
PDMSS
f
t
t
PDM
MAX
PHL
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup Time, Fast Slew Rate
Setup Time, Slow Slew Rate
Hold Time, Fast Slew Rate
Hold Time, Slow Slew Rate
Parameter
CLK and CLK to Q
CLK and CLK to Q (simultaneous switching)
RESET to Q
(3,5)
(2,5)
(3, 5)
(1)
(4, 5)
(2)
ACT
Data Before CLK↑, CLK↓
Data Before CLK↑, CLK ↓
max., after RESET is taken HIGH.
Package
TSSOP, VFQFPN
TSSOP
VFQFPN
TSSOP
VFQFPN
TSSOP, VFQFPN
5
Min.
0.65
0.75
0.75
INACT
2.5
0.9
—
—
—
PC1600 - PC2700
max., after RESET is taken LOW.
Max.
200
—
22
22
—
—
—
—
PC1600 - PC2700
Min.
200
1.1
1.1
—
—
—
COMMERCIAL TEMPERATURE RANGE
Max.
2.4
2.2
2.7
2.5
—
Min.
0.65
0.75
0.65
5
2.5
0.8
—
—
—
PC3200
Min.
220
1.1
1.1
—
—
—
PC3200
((TBD))
Max.
220
Max.
—
22
22
—
—
—
—
2.2
1.8
2.5
—
5
MHz
Unit
MHz
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns