LPC1113FHN33/203,5 NXP Semiconductors, LPC1113FHN33/203,5 Datasheet - Page 440

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LPC1113FHN33/203,5

Manufacturer Part Number
LPC1113FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 24 kB flash up to 8kB SRAM
Manufacturer
NXP Semiconductors
Datasheet

Specifications of LPC1113FHN33/203,5

Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1113
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
24 KB
Data Ram Size
4 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Factory Pack Quantity
260
NXP Semiconductors
UM10398
User manual
26.10.1.3 Flash Module Status register
26.10.1.4 Flash Module Status Clear register
26.10.2
The read-only FMSTAT register provides a means of determining when signature
generation has completed. Completion of signature generation can be checked by polling
the SIG_DONE bit in FMSTAT. SIG_DONE should be cleared via the FMSTATCLR
register before starting a signature generation operation, otherwise the status might
indicate completion of a previous operation.
Table 415. Flash module Status register (FMSTAT - 0x4003 CFE0) bit description
The FMSTATCLR register is used to clear the signature generation completion flag.
Table 416. Flash Module Status Clear register (FMSTATCLR - 0x0x4003 CFE8) bit description
Algorithm and procedure for signature generation
Signature generation
A signature can be generated for any part of the flash contents. The address range to be
used for signature generation is defined by writing the start address to the FMSSTART
register, and the stop address to the FMSSTOP register.
The signature generation is started by writing a ‘1’ to the SIG_START bit in the FMSSTOP
register. Starting the signature generation is typically combined with defining the stop
address, which is done in the STOP bits of the same register.
The time that the signature generation takes is proportional to the address range for which
the signature is generated. Reading of the flash memory for signature generation uses a
self-timed read mechanism and does not depend on any configurable timing settings for
the flash. A safe estimation for the duration of the signature generation is:
Bit
1:0
2
31:3
Bit
1:0
2
31:3
Duration = int((60 / tcy) + 3) x (FMSSTOP - FMSSTART + 1)
Symbol
-
SIG_DONE
-
Symbol
-
SIG_DONE_CLR Writing a 1 to this bits clears the signature generation
-
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 24 September 2012
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When 1, a previously started signature generation has
completed. See FMSTATCLR register description for clearing this
flag.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Chapter 26: LPC111x/LPC11Cxx Flash programming firmware
Description
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
completion flag (SIG_DONE) in the FMSTAT register.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
UM10398
© NXP B.V. 2012. All rights reserved.
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Reset
value
NA
0
NA
Reset
value
NA
0
NA

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