LPC1111FHN33/203,5 NXP Semiconductors, LPC1111FHN33/203,5 Datasheet - Page 230
LPC1111FHN33/203,5
Manufacturer Part Number
LPC1111FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 8kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
Microwire format is very similar to SPI format, except that transmission is half-duplex
instead of full-duplex, using a master-slave message passing technique. Each serial
transmission begins with an 8-bit control word that is transmitted from the SPI/SSP to the
off-chip slave device. During this transmission, no incoming data is received by the
SPI/SSP. After the message has been sent, the off-chip slave decodes it and, after waiting
one serial clock after the last bit of the 8-bit control message has been sent, responds with
the required data. The returned data is 4 to 16 bit in length, making the total frame length
anywhere from 13 to 25 bits.
In this configuration, during idle periods:
A transmission is triggered by writing a control byte to the transmit FIFO.The falling edge
of CS causes the value contained in the bottom entry of the transmit FIFO to be
transferred to the serial shift register of the transmit logic, and the MSB of the 8-bit control
frame to be shifted out onto the SO pin. CS remains LOW for the duration of the frame
transmission. The SI pin remains tristated during this transmission.
The off-chip serial slave device latches each control bit into its serial shifter on the rising
edge of each SK. After the last bit is latched by the slave device, the control byte is
decoded during a one clock wait-state, and the slave responds by transmitting data back
to the SPI/SSP. Each bit is driven onto SI line on the falling edge of SK. The SPI/SSP in
Fig 41. Microwire frame format (single transfer)
Fig 42. Microwire frame format (continuous transfers)
•
•
•
The SK signal is forced LOW.
CS is forced HIGH.
The transmit data line SO is arbitrarily forced LOW.
CS
SO
SK
SI
CS
SO
SK
SI
All information provided in this document is subject to legal disclaimers.
LSB
MSB
0
Rev. 12 — 24 September 2012
MSB
of output data
4 to 16 bits
8-bit control
LSB
MSB
Chapter 14: LPC111x/LPC11Cxx SPI0/1 with SSP
LSB
8-bit control
0
MSB
of output data
4 to 16 bits
LSB
LSB
MSB
of output data
4 to 16 bits
UM10398
© NXP B.V. 2012. All rights reserved.
LSB
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