LPC1111FHN33/203,5 NXP Semiconductors, LPC1111FHN33/203,5 Datasheet - Page 494
LPC1111FHN33/203,5
Manufacturer Part Number
LPC1111FHN33/203,5
Description
ARM Microcontrollers - MCU Cortex-M0 8kB flash up to 4 kB SRAM
Manufacturer
NXP Semiconductors
Datasheet
1.LPC1113FHN333035.pdf
(538 pages)
Specifications of LPC1111FHN33/203,5
Rohs
yes
Core
ARM Cortex M0
Processor Series
LPC1111
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
8 KB
Data Ram Size
8 KB
On-chip Adc
Yes
Operating Supply Voltage
1.8 V to 3.6 V
Operating Temperature Range
- 65 C to + 150 C
Package / Case
HVQFN-33
Mounting Style
SMD/SMT
Interface Type
I2C, SPI, UART
Number Of Programmable I/os
42
Number Of Timers
4
Program Memory Type
Flash
Factory Pack Quantity
260
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NXP Semiconductors
UM10398
User manual
28.5.7.10.1 Syntax
28.5.7.10.2 Operation
28.5.7.10.3 Restrictions
28.5.7.10.4 Condition flags
28.5.7.10 SVC
28.5.7.8.4 Condition flags
28.5.7.8.5 Examples
28.5.7.9.1 Syntax
28.5.7.9.2 Operation
28.5.7.9.3 Restrictions
28.5.7.9.4 Condition flags
28.5.7.9.5 Examples
28.5.7.9 SEV
This instruction does not change the flags.
Send Event.
SEV
SEV causes an event to be signaled to all processors within a multiprocessor system. It
also sets the local event register, see
See also
There are no restrictions.
This instruction does not change the flags.
Supervisor Call.
SVC #imm
where:
The SVC instruction causes the SVC exception.
imm is ignored by the processor. If required, it can be retrieved by the exception handler to
determine what service is being requested.
There are no restrictions.
This instruction does not change the flags.
NOP ; No operation
SEV ; Send Event
imm is an integer in the range 0-255.
Section
Chapter 28: LPC111x/LPC11Cxx Appendix: ARM Cortex-M0 reference
All information provided in this document is subject to legal disclaimers.
28–28.5.7.11.
Rev. 12 — 24 September 2012
Section
28–28.4.5.
UM10398
© NXP B.V. 2012. All rights reserved.
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