1893CFLFT IDT, 1893CFLFT Datasheet - Page 30

• Manufacturer Part Number: 1893CFLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CFLFT

• Rohs: yes
• Part # Aliases: ICS1893CFLFT

6.3.3 PCS/PMA Transmit Modules
6.3.3.1 PCS Transmit Module
6.3.3.2 PMA Transmit Module
6.3.4 PCS/PMA Receive Modules
6.3.4.1 PCS Receive Module
ICS1893CK-40, Rev. C, 06/02/09
Both the PCS and PMA sublayers have Transmit modules.
The ICS1893CK-40 PCS Transmit module accepts nibbles from the MAC Interface and converts the
nibbles into 5-bit ‘code groups’ (referred to here as ‘symbols’). In addition, the PCS Transmit module
performs a parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit
stream to the PMA sublayer.
The first 16 nibbles of each MAC Frame represent the Frame Preamble. The PCS replaces the first two
nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/. After
receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the Frame
an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1893CK-40 PCS does not alter any
other data included within the Frame.)
The PCS Transmit module also performs collision detection. In compliance with the ISO/IEC specification,
when the transmission and reception of data occur simultaneously and the ICS1893CK-40 is in:
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The ICS1893CK-40 PMA Transmit module accepts a serial bit stream from its PCS and converts the data
into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1893CK-40 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface.
Both the PCS and PMA sublayers have Receive modules.
The ICS1893CK-40 PCS Receive module accepts both a serial bit stream and a clock signal from the PMA
sublayer. The PCS Receive module converts the bit stream from a serial format to a parallel format and
then processes the data to detect the presence of a carrier.
When a link is in the idle state, the PCS Receive module receives IDLE symbols. (All bits are logic one.)
Upon receiving two non-contiguous zeros in the bit stream, the PCS Receive module examines the
ensuing bits and attempts to locate the Start-of-Stream Delimiter (SSD), that is, the /J/K/ symbols.
Upon verification of a valid SSD, the PCS Receive module substitutes the first two standard nibbles of a
Frame Preamble for the detected SSD. In addition, the PCS Receive module uses the SSD to begin
framing the ensuing data into 5-bit code symbols. The final PCS Receive module performs 4B/5B decoding
on the symbols and then synchronously passes the resulting nibbles to the MAC Interface.
The Receive state machine continues to accept PMA data, convert it from serial to parallel format, frame it,
decode it, and pass it to the MAC Interface. During this time, the Receive state machine alternates between
Receive and Data States. It continues this process until detecting one of the following:
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Half-duplex mode, the ICS1893CK-40 asserts the collision detection signal (COL).
Full-duplex mode, COL is always FALSE.
An End-of-Stream Delimiter (ESD, that is, the /T/R/ symbols)
An error
A premature end (IDLEs)
ICS1893CK-40 Data Sheet - Release
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
30
Chapter 6 Functional Blocks
June 2009