1893CFLFT IDT, 1893CFLFT Datasheet - Page 40

• Manufacturer Part Number: 1893CFLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CFLFT

• Rohs: yes
• Part # Aliases: ICS1893CFLFT

6.6.2.1 Management Frame Preamble
6.6.2.2 Management Frame Start
6.6.2.3 Management Frame Operation Code
6.6.2.4 Management Frame PHY Address
ICS1893CK-40, Rev. C, 06/02/09
Note:
Table 6-1. Management Frame Structure Summary
The ICS1893CK-40 continually monitors its serial management interface for either valid data or a
Management Frame (MF) Preamble, based upon the setting of the MF Preamble Suppression bit, 1.6.
When the MF Preamble Suppression is disabled, an ICS1893CK-40 waits for a MF Preamble which
indicates the start of an STA transaction. A Management Frame Preamble is a pattern of 32 contiguous
logic one bits on the MDIO pin, along with 32 corresponding clock cycles on the MDC pin.
The ICS1893CK-40 supports the Management Frame (MF) Preamble Suppression capability on its
Management Interface, thereby providing a method to shorten the Management Frame and provide an STA
with faster access to the Management Registers.
The ability to process Management Frames that do not have a preamble is provided by the Management
Frame Preamble Suppression bit, (bit 1.6 in the ICS1893CK-40’s Status Register). This is an ISO/IEC
defined status bit that is intended to provide an indication of whether or not a PHY supports the MF
Preamble Suppression feature. In order to maintain backward compatibility with the ICS1890, which did not
support MF Preamble Suppression, the ICS1893CK-40 MF Preamble Suppression bit is a Command
Override Write bit which defaults to a logic zero. An STA can enable MF Preamble Suppression by writing
a logic one to bit 1.6 subsequent to a write of logic one to the Command Override bit, 16.15. For an
explanation of the Command Override Write bits, see
A valid Management Frame includes a start-of-frame delimiter, SFD, immediately following the preamble.
The SFD bit pattern is 01b and is synchronous with two clock cycles on the MDC pin.
A valid Management Frame includes an operation code (OP) immediately following the start-of-frame
delimiter. There are two valid operation codes: one for reading from a management register, 10b, and one
for writing to a management register, 01b. The ICS1893CK-40 does not respond to the codes 00b and 11b,
which the ISO/IEC specification defines as invalid.
The two-wire, Serial Management Interface is specified to allow busing (that is, the sharing of the two wires
among multiple PHYs). The Management Frame includes a 5-bit PHY Address field, PHYAD, allowing for
32 unique addresses. An STA uniquely identifies each of the PHYs that share a single serial management
interface by using this 5-bit PHY Address field, PHYAD.
PRE
SFD
OP
PHYAD
REGAD
TA
DATA
Acronym
The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE
periods are not part of the Management Frame Structure.
ICS1893CK-40 Data Sheet - Release
Preamble (Bit 1.6)
Start of Frame
Operation Code
PHY Address (Bits 16.10:6)
Register Address
Turnaround
Data
Frame Field
Frame Function
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
40
11..11
01
10/01 (read/write)
AAAAA
RRRRR
Z0/10 (read/write)
DDD..DD
Section 7.1.2, “Management Register Bit
Data
32 ones
2 bits
2 bits
5 bits
5 bits
2 bits
16 bits
Comment
Chapter 6 Functional Blocks
Access”.
June 2009