1893CFLFT IDT, 1893CFLFT Datasheet - Page 35

• Manufacturer Part Number: 1893CFLFT
• Description: Ethernet ICs 3.3V 10/100 BASE TX INTEGRATED PHYCEIVER
• Manufacturer: IDT

Specifications of 1893CFLFT

• Rohs: yes
• Part # Aliases: ICS1893CFLFT

6.5.2 10Base-T Operation: Clock Synthesis
6.5.3 10Base-T Operation: Clock Recovery
6.5.4 10Base-T Operation: Idle
6.5.5 10Base-T Operation: Link Monitor
ICS1893CK-40, Rev. C, 06/02/09
During 10Base-T data reception, a Manchester Decoder translates the serial bit stream obtained from the
Twisted-Pair Receiver (MDI) into an NRZ bit stream. The Manchester Decoder then passes the data to the
MAC Interface in parallel format.
Manchester-encoded signals have the following advantages:
•
•
The primary disadvantage in using Manchester-encoded signals is that it doubles the data rate, making it
operationally prohibitive for 100-MHz operations.
The ICS1893CK-40 synthesizes the clocks required for synchronizing data transmission. In 10Base-T
mode, the MAC Interface provides a 10M MII (Media Independent Interface):
•
The ICS1893CK-40 recovers its receive clock from the Manchester-encoded data stream obtained from its
Twisted-Pair Receiver using a phase-locked loop (PLL). The ICS1893CK-40 then uses this recovered clock
for synchronizing data transmission between itself and the MAC. Receive-clock PLL acquisitions begin with
reception of the MAC Frame Preamble and continue as long as the ICS1893CK-40 is receiving data.
An ICS1893CK-40 transmits Normal Link Pulses on its MDI in the absence of data. During this time the link is
Idle, and the ICS1893CK-40 periodically transmits link pulses at a rate of one link pulse every 16 ms in
compliance with the ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1893CK-40 continues transmitting
link pulses even while receiving data.
When an ICS1893CK-40 is in 10Base-T mode, its Link Monitor Function observes the data received by the
10Base-T Twisted-Pair Receiver to determine the link status. The results of this continual monitoring are
stored in the Link Status bit. The Station Management entity (STA) can access the Link Status bit in either
the Status Register (bit 1.2) or the QuickPoll Detailed Status Register (bit 17.0).
When the Link Status bit is:
•
•
The ICS1893CK-40 Link Status bit is a latching low (LL) bit. (For more information on latching high and
latching low bits, see
The criteria used by the Link Monitor Function to declare a link either valid or invalid depends upon these
factors: the present state of the link, whether its Smart Squelch function is enabled, and the incoming data.
Every bit period has an encoded clock.
The split-phase nature of the signal always provides a zero DC level regardless of the data (that is, there
is no baseline wander phenomenon).
10M MII interface, the ICS1893CK-40 synthesizes a 2.5-MHz clock for nibble-wide transactions
Zero, either a valid link is not established or the link is momentarily dropped since either the last read of
the Link Status bit or the last reset of the ICS1893CK-40.
One, a valid link is established.
ICS1893CK-40 Data Sheet Rev. C - Release
Section 7.1.4.1, “Latching High Bits”
Copyright © 2009, Integrated Device Technology, Inc.
All rights reserved.
35
and
Section 7.1.4.2, “Latching Low
Chapter 6 Functional Blocks
Bits”.)
June 2009