KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 16

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Micrel, Inc.
KSZ8851-16MLL/MLLI
issue a wakeup command which is a read cycle to read the Globe Reset Register (GRR at 0x26) to wake up the
KSZ8851-16MLL from the low power state to the normal power state in case the auto-wakeup enable bit[7] is disabled.
When KSZ8851-16MLL is at normal power state, it is able to transmit or receive packet from the cable.
Soft Power Down Mode
The soft power down mode is entered by setting bit[1:0]=10 in PMECR register. When KSZ8851-16MLL is in this mode,
all PLL clocks are disabled, the PHY and the MAC are off, all internal registers value will not change, and the host
interface is only used to wake-up this device from current soft power down mode to normal operation mode.
In order to go back the normal operation mode from this soft power down mode, the only way to leave this mode is
through a host wake-up command which the CPU issues to read the Globe Reset Register (GRR at 0x26).
Power Saving Mode
The power saving mode is entered when auto-negotiation mode is enabled, cable is disconnected, and by setting
bit[1:0]=11 in PMECR register and bit [10]=1 in P1SCLMD register. When KSZ8851M is in this mode, all PLL clocks are
enabled, MAC is on, all internal registers value will not change, and host interface is ready for CPU read or write. In this
mode, it mainly controls the PHY transceiver on or off based on line status to achieve power saving. The PHY remains
transmitting and only turns off the unused receiver block. Once activity resumes due to plugging a cable or attempting by
the far end to establish link, the KSZ8851M can automatically enabled the PHY power up to normal power state from
power saving mode.
During this power saving mode, the host CPU can program the bit[1:0] in PMECR register and set bit[10]=0 in P1SCLMD
register to transit the current power saving mode to any one of the other three power management operation modes.
Wake-on-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device is
pre-programmed by the policy owner or other software with information on how to identify wake frames from other network
traffic. The KSZ8851-16MLL controller can be programmed to notify the host of the wake-up frame detection with the
assertion of the interrupt signal (INTRN) or assertion of the power management event signal (PME).
A wake-up event is a request for hardware and/or software external to the network device to put the system into a
powered state (working).
A wake-up signal is caused by:
1. Detection of energy signal over a pre-configured value (bit 2 in ISR register)
2. Detection of a linkup in the network link state (bit 3 in ISR register)
3. Receipt of a Magic Packet (bit 4 in ISR register)
4. Receipt of a network wake-up frame (bit 5 in ISR register)
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these in
their own way.
Detection of Energy
The energy is detected from the cable and is continuously presented for a time longer than pre-configured value,
especially when this energy change may impact the level at which the system should re-enter to the normal power state.
Detection of Linkup
Link status wake events are useful to indicate a linkup in the network’s connectivity status.
Wake-up Packet
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.
The KSZ8851-16MLL supports up to four users defined wake-up frames as below:
1. Wake-up frame 0 is defined in wakeup frame registers (0x30 – 0x3B) and is enabled by bit 0 in wakeup frame control
register (0x2A).
2. Wake-up frame 1 is defined in wakeup frame registers (0x40 – 0x4B) and is enabled by bit 1 in wakeup frame control
register (0x2A).
May 2012
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M9999-050112-2.1