KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 27

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

supported. The BIU, however, provides flexible asynchronous interfacing to communicate with various applications and
architectures. No additional address latch is required. The BIU qualifies both CSN (Chip Select) pin and WRN (Write
Enable) pin to write the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address A[7:0] value (in 8-bit mode) into
KSZ8851-16MLL when CMD (Command type) pin is high. The BIU qualifies both CSN (Chip Select) pin and RDN (Read
Enable) or WRN (Write Enable) pin to read or write the SD[15:0] data value from or to KSZ8851-16MLL when CMD
(Command type) pin is low.
In order for software to read back the previous CMD register write value when CMD is “1”, the BIU qualifies both CSN
(Chip Select) pin and RDN (Read Enable) pin to read the Address A[7:2] and BE[3:0] value (in 16-bit mode) or Address
A[7:0] value (in 8-bit mode) back from KSZ8851-16MLL when CMD (Command type) pin is high.
BIU Summation
Figure 6 shows the connection for different data bus sizes. Also refer to reference schematics in hardware design
package.
All of control and status registers in the KSZ8851-16MLL are accessed indirectly depending on CMD (Command type)
pin. The command sequence to access the specified control or status register is to write the register’s address (when
CMD=1) then read or write this register data (when CMD=0). If both RDN and WRN signals in the system are only used
for KSZ8851-16MLL, the CSN pin can be forced to active low to simplify the system design. The CMD pin can be
connected to host address line HA0 for 8-bit bus mode or HA1 for 16-bit bus mode.
Note: In 16-bit bus mode, the SD1 bit must set to “1” when CMD = 1 during DMA access.
Queue Management Unit (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It has
built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue). Each
queue contains 12KB for RXQ and 6KB for TXQ of memory with back-to-back, non-blocking frame transfer performance.
It provides a group of control registers for system control, frame status registers for current packet transmit/receive status,
and interrupts to inform the host of the real time TX/RX status.
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in the following Table 5. The first word contains the control information
for the frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data
follows. The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon
whether hardware CRC checksum generation is enabled in TXCR (bit 1) register.
Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue memory,
thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the TXSR
May 2012
Micrel, Inc.
Figure 6. KSZ8851-16MLL 8-Bit and 16-Bit Data Bus Connections
Data Bus
Data Bus
Shared
Shared
SD10
SD10
SD11
SD11
SD12
SD12
SD13
SD13
SD14
SD14
SD15
SD15
SD0
SD0
SD1
SD1
SD2
SD2
SD3
SD3
SD4
SD4
SD5
SD5
SD6
SD6
SD7
SD7
SD8
SD8
SD9
SD9
Pin 1 (P1LED1) = 1K Pull
Pin 1 (P1LED1) = 1K Pull
8-Bit Bus Mode
8-Bit Bus Mode
CMD=0
CMD=0
Down during RESET
Down during RESET
“Low”
“Low”
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
CMD=1
CMD=1
“High”
“High”
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A0
A0
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
27
Pin 1 (P1LED1) = NC or
Pin 1 (P1LED1) = NC or
16-Bit Bus Mode
16-Bit Bus Mode
CMD=0
CMD=0
Pull Up during RESET
Pull Up during RESET
“Low”
“Low”
D10
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
CMD=1
CMD=1
“High”
“High”
BE0
BE0
BE1
BE1
BE2
BE2
BE3
BE3
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
-
-
-
-
-
-
-
-
-
-
-
-
KSZ8851-16MLL/MLLI
M9999-050112-2.1