KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 5

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

CPU Interface I/O Registers ...............................................................................................................................36
Register Map: MAC, PHY and QMU...................................................................................................................43
May 2012
Micrel, Inc.
Driver Routine for Transmit Packet from Host Processor to KSZ8851-16MLL ...........................................29
Receive Queue (RXQ) Frame Format ........................................................................................................32
Frame Receiving Path Operation in RXQ ...................................................................................................32
Driver Routine for Receive Packet from KSZ8851-16MLL to Host Processor ............................................33
EEPROM Interface .....................................................................................................................................34
Loopback Support.......................................................................................................................................35
Near-end (Remote) Loopback ....................................................................................................................35
Far-end (Local) Loopback...........................................................................................................................35
I/O Registers ...............................................................................................................................................36
Internal I/O Registers Space Mapping ........................................................................................................37
Bit Type Definition.......................................................................................................................................43
0x00 – 0x07: Reserved ...............................................................................................................................43
Chip Configuration Register (0x08 – 0x09): CCR .......................................................................................43
0x0A – 0x0F: Reserved ..............................................................................................................................43
Host MAC Address Registers: MARL, MARM and MARH..........................................................................43
Host MAC Address Register Low (0x10 – 0x11): MARL.............................................................................44
Host MAC Address Register Middle (0x12 – 0x13): MARM........................................................................44
Host MAC Address Register High (0x14 – 0x15): MARH ...........................................................................44
0x16 – 0x1F: Reserved...............................................................................................................................44
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................44
EEPROM Control Register (0x22 – 0x23): EEPCR ....................................................................................44
Memory BIST Info Register (0x24 – 0x25): MBIR.......................................................................................45
Global Reset Register (0x26 – 0x27): GRR ................................................................................................45
0x28 – 0x29: Reserved ...............................................................................................................................46
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................46
0x2C – 0x2F: Reserved ..............................................................................................................................46
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 .....................................................................46
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 .....................................................................46
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 .............................................................47
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 .............................................................47
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 .............................................................47
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3.............................................................47
0x3C – 0x3F: Reserved ..............................................................................................................................47
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 .....................................................................47
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 .....................................................................47
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 .............................................................48
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 .............................................................48
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 .............................................................48
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3.............................................................48
0x4C – 0x4F: Reserved ..............................................................................................................................48
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 .....................................................................48
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 .....................................................................48
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 .............................................................49
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 .............................................................49
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 .............................................................49
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KSZ8851-16MLL/MLLI
M9999-050112-2.1