KSZ8851-16MLLU TR Micrel, KSZ8851-16MLLU TR Datasheet - Page 32

• Manufacturer Part Number: KSZ8851-16MLLU TR
• Description: Ethernet ICs Single-Port Ethernet Controller (Automotive Grade)
• Manufacturer: Micrel

Specifications of KSZ8851-16MLLU TR

• Rohs: yes
• Product: Ethernet Controllers
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT

Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 9. The first word contains the status information for the frame
received. The second word is the total number of bytes of the RX frame. Following that is the packet data area. The
packet data area holds the frame itself. It includes the CRC checksum.
Frame Receiving Path Operation in RXQ
This section describes the typical register settings for receiving packets from KSZ8851-16MLL to host processor with
generic bus interface. User can use the default value for most of the receive registers. The following Table 10 describes
all registers which need to be set and used for receiving single or multiple frames.
May 2012
Register Name[bit](offset)
RXCR1(0x74)
RXCR2(0x76)
RXFHSR[15:0](0x7C)
RXFHBCR[11:0](0x7E)
RXQCR[12:3](0x82)
RXFDPR[14](0x86)
RXDTTR[15:0](0x8C)
RXDBCTR[15:0](0x8E)
IER[13](0x90)
ISR[15:0](0x92)
RXFCTR[15:8](0x9C)
RXFCTR[7:0](0x9C)
Micrel, Inc.
Packet Memory
Address Offset
0
2
4 - up
Bit 15
2
Status Word
(High byte and low byte need to swap in Big-Endian mode. Also see description in RXFHSR register)
Byte Count
(High byte and low byte need to swap in Big-Endian mode. Also see description in RXFHBCR register)
Receive Packet Data
(maximum size is 2000)
nd
Byte
Set receive control function as below:
Set RXCR1[10] to enable receiving flow control. Set RXCR1[0] to enable receiving block operation.
Set receive checksum check for ICMP, UDP, TCP and IP packet.
Set receive address filtering scheme as shown in the Table 3.
This register (read only) indicates the current received frame header status information.
This register (read only) indicates the current received frame header byte count information.
Set RXQ control function as below:
Set bit 3 to start DMA access from host CPU either read (receive frame data) or write (transmit data
frame). Set bit 4 to automatically enable RXQ frame buffer dequeue. Set bit 5 to enable RX frame count
threshold and read bit 10 for status. Set bit 6 to enable RX data byte count threshold and read bit 11 for
status. Set bit 7 to enable RX frame duration timer threshold and read bit 12 for status. Set bit 9 enable
RX IP header two-byte offset.
Set bit 14 to enable RXQ address register increments automatically on accesses to the data register.
To program received frame duration timer value. When Rx frame duration in RXQ exceeds this
threshold in 1uS interval count and bit 7 of RXQCR register is set to 1, the KSZ8851-16MLL will
generate RX interrupt in ISR[13] and indicate the status in RXQCR[12].
To program received data byte count value. When the number of received bytes in RXQ exceeds this
threshold in byte count and bit 6 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX
interrupt in ISR[13] and indicate the status in RXQCR[11].
Set bit 13 to enable receive interrupt in Interrupt Enable Register.
Write 1 (0xFFFF) to clear all interrupt status bits after interrupt occurred in Interrupt Status Register.
Rx frame count read only. To indicate the total received frame in RXQ frame buffer when receive
interrupt (bit 13 in ISR) occurred.
To program received frame count value. When the number of received frames in RXQ exceeds this
threshold value and bit 5 of RXQCR register is set to 1, the KSZ8851-16MLL will generate RX interrupt
in ISR[13] and indicate the status in RXQCR[10].
Table 10. Registers Setting for Receive Function Block
Table 9. Frame Format for Receive Queue
1
st
32
Bit 0
Byte
Description
KSZ8851-16MLL/MLLI
M9999-050112-2.1