PCAL9555APW,118 NXP Semiconductors, PCAL9555APW,118 Datasheet - Page 13

• Manufacturer Part Number: PCAL9555APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
PCAL9555A
Product data sheet
6.3 I/O port
6.4 Power-on reset
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a
high-impedance input. The input voltage may be raised above V
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the
Output port register. In this case, there are low-impedance paths between the I/O pin and
either V
recommended levels for proper operation.
When power (from 0 V) is applied to V
PCAL9555A in a reset condition until V
condition is released and the PCAL9555A registers and I
initializes to their default states. After that, V
up to the operating voltage for a power-reset cycle. See
requirements”.
Fig 6. Simplified schematic of the I/Os (P0_0 to P0_7, P1_0 to P1_7)
configuration
shift register
shift register
shift register
write polarity
shift register
write pulse
latch pulse
write input
read pulse
data from
data from
data from
data from
PULL-UP/PULL-DOWN
pulse
pulse
write
DD
At power-on reset, all registers return to default values.
or V
CONTROL
configuration
register
input latch
register
SS
D
CK
D
CK
All information provided in this document is subject to legal disclaimers.
. The external voltage applied to this I/O pin should not exceed the
FF
FF
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
Q
Q
Q
Rev. 1 — 3 October 2012
output port
register
V
D
CK
DD
FF
100 kΩ
Q
polarity inversion
register
D
CK
DD
DD
FF
input port
register
D
CK
, an internal power-on reset holds the
has reached V
Q
FF
DD
Q
must be lowered to below V
Q1
Q2
read pulse
Section 8.3 “Power-on reset
POR
2
C-bus/SMBus state machine
. At that time, the reset
DD
INTERRUPT
PCAL9555A
MASK
to a maximum of 5.5 V.
ESD
protection
diode
ESD
protection
diode
© NXP B.V. 2012. All rights reserved.
input port
latch
D
EN
LATCH
PORF
output port
register data
V
P0_0 to P0_7
P1_0 to P1_7
V
input port
register data
to INT
Q
DD
SS
and back
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