PCAL9555APW,118 NXP Semiconductors, PCAL9555APW,118 Datasheet - Page 5

• Manufacturer Part Number: PCAL9555APW,118
• Description: Interface - I/O Expanders 16b I2C BUS INTERUPT
• Manufacturer: NXP Semiconductors

Specifications of PCAL9555APW,118

• Rohs: yes
• Maximum Operating Frequency: 100 kHz
• Operating Supply Voltage: 1.65 V to 5.5 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-24
• Operating Current: 160 mA
• Output Current: 25 mA
• Power Dissipation: 200 mW
• Product Type: I/O Expanders
• Factory Pack Quantity: 2500

NXP Semiconductors
6. Functional description
PCAL9555A
Product data sheet
6.2.1 Pointer register and command byte
6.1 Device address
6.2 Registers
Table 3.
[1]
[2]
[3]
Refer to
A2, A1 and A0 are the hardware address package pins and are held to either HIGH
(logic 1) or LOW (logic 0) to assign one of the eight possible slave addresses. The last bit
of the slave address (R/W) defines the operation (read or write) to be performed. A HIGH
(logic 1) selects a read operation, while a LOW (logic 0) selects a write operation.
Following the successful acknowledgement of the address byte, the bus master sends a
command byte, which is stored in the Pointer register in the PCAL9555A. The lower
three bits of this data byte state the operation (read or write) and the internal registers
(Input, Output, Polarity Inversion, or Configuration) that will be affected. Bit 6 in
conjunction with the lower four bits of the Command byte are used to point to the
extended features of the device (Agile I/O). This register is write only.
Symbol
P1_7
A0
SCL
SDA
V
Fig 4. PCAL9555A device address
DD
HWQFN24 package die supply ground is connected to both V
be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board
level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad
on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the
PCB in the thermal pad region.
Pins P0_0 to P0_7 correspond to bits P0.0 to P0.7. At power-up, all I/O are configured as high-impedance
inputs.
Pins P1_0 to P1_7 correspond to bits P1.0 to P1.7. At power-up, all I/O are configured as high-impedance
inputs.
[3]
Figure 1 “Block diagram of
Pin
TSSOP24
20
21
22
23
24
Pin description
All information provided in this document is subject to legal disclaimers.
Low-voltage 16-bit GPIO with Agile I/O, interrupt and weak pull-up
Rev. 1 — 3 October 2012
HWQFN24
17
18
19
20
21
…continued
0
1
fixed
Type
I/O
I
I
I/O
power
PCAL9555A”.
slave address
0
0
Description
Port 1 input/output 7.
Address input 0. Connect directly to V
Serial clock bus. Connect to V
pull-up resistor.
Serial data bus. Connect to V
pull-up resistor.
Supply voltage.
A2
selectable
hardware
A1
SS
A0
002aaf819
pin and exposed center pad. V
R/W
PCAL9555A
© NXP B.V. 2012. All rights reserved.
DD
DD
through a
through a
DD
SS
or V
pin must
5 of 46
SS
.