C8051F997-GUR Silicon Labs, C8051F997-GUR Datasheet - Page 68

• Manufacturer Part Number: C8051F997-GUR
• Description: 8-bit Microcontrollers - MCU 8kB 14-CH CDC
• Manufacturer: Silicon Labs

Specifications of C8051F997-GUR

• Rohs: yes
• Core: 8051
• Processor Series: C8051
• Data Bus Width: 8 bit

C8051F99x-C8051F98x
5.2.3. Burst Mode
Burst Mode is a power saving feature that allows ADC0 to remain in a low power state between
conversions. When Burst Mode is enabled, ADC0 wakes from a low power state, accumulates 1, 4, 8, 16,
32, or 64 using an internal Burst Mode clock (approximately 20 MHz), then re-enters a low power state.
Since the Burst Mode clock is independent of the system clock, ADC0 can perform multiple conversions
then enter a low power state within a single system clock cycle, even if the system clock is slow (e.g.
32.768 kHz), or suspended.
Burst Mode is enabled by setting BURSTEN to logic 1. When in Burst Mode, AD0EN controls the ADC0
idle power state (i.e. the state ADC0 enters when not tracking or performing conversions). If AD0EN is set
to logic 0, ADC0 is powered down after each burst. If AD0EN is set to logic 1, ADC0 remains enabled after
each burst. On each convert start signal, ADC0 is awakened from its Idle Power State. If ADC0 is powered
down, it will automatically power up and wait the programmable Power-Up Time controlled by the
AD0PWR bits. Otherwise, ADC0 will start tracking and converting immediately. Figure 5.3 shows an
example of Burst Mode Operation with a slow system clock and a repeat count of 4.
When Burst Mode is enabled, a single convert start will initiate a number of conversions equal to the repeat
count. When Burst Mode is disabled, a convert start is required to initiate each conversion. In both modes,
the ADC0 End of Conversion Interrupt Flag (AD0INT) will be set after “repeat count” conversions have
been accumulated. Similarly, the Window Comparator will not compare the result to the greater-than and
less-than registers until “repeat count” conversions have been accumulated.
In Burst Mode, tracking is determined by the settings in AD0PWR and AD0TK. The default settings for
these registers will work in most applications without modification; however, settling time requirements may
need adjustment in some applications. Refer to “5.2.4. Settling Time Requirements” on page 69 for more
details.
Notes:


68
S yste m C lo ck
C o n ve rt S ta rt
A D 0 T M = 1
A D 0 E N = 0
A D 0 T M = 0
A D 0 E N = 0
Setting AD0TM to 1 will insert an additional 3 SAR clocks of tracking before each conversion,
regardless of the settings of AD0PWR and AD0TK.
When using Burst Mode, care must be taken to issue a convert start signal no faster than once every
four SYSCLK periods. This includes external convert start signals.
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4
T = T ra ckin g se t b y A D 0 T K
T 3 = T ra ckin g se t b y A D 0 T M (3 S A R clo cks)
C = C o n ve rtin g
P o w e re d
P o w e re d
D o w n
D o w n
P o w e r-U p
a n d T ra ck
P o w e r-U p
a n d T ra ck
A D 0 P W R
T
3
C
C
T C
T
T
3
Rev. 1.1
T C
C
A D 0 T K
T
T C
T
3
C
T
T
3
P o w e re d
C
D o w n
P o w e re d
D o w n
P o w e r-U p
a n d T ra ck
P o w e r-U p
a n d T ra ck
T C ..
T C ..