CD40106BCN_Q Fairchild Semiconductor, CD40106BCN_Q Datasheet

CD40106BCN_Q

Manufacturer Part Number

CD40106BCN_Q

Description

Inverters Hex Schmitt Trigger

Manufacturer

Fairchild Semiconductor

Datasheet

1.CD40106BCN_Q.pdf (6 pages)

Specifications of CD40106BCN_Q

Product Category

Inverters

Number Of Circuits

Logic Family

CD4K

Logic Type

CMOS

High Level Output Current

- 4.2 mA

Low Level Output Current

4.2 mA

Propagation Delay Time

400 ns, 200 ns, 160 ns

Supply Voltage - Max

15 V

Supply Voltage - Min

3 V

Maximum Operating Temperature

+ 125 C

Package / Case

PDIP-14

Mounting Style

Through Hole

Operating Supply Voltage

3 V to 15 V

Current page: 1 of 6
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CD40106BCM

CD40106BCN

CD40106BC

Hex Schmitt Trigger

General Description

The CD40106BC Hex Schmitt Trigger is a monolithic com-

plementary MOS (CMOS) integrated circuit constructed

with N and P-channel enhancement transistors. The posi-

tive and negative-going threshold voltages, V

show low variation with respect to temperature (typ

0.0005V/ C at V

All inputs are protected from damage due to static dis-

charge by diode clamps to V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

is guaranteed.

Pin Assignments for DIP and SOIC

Package Number

10V), and hysteresis, V

Top View

M14A

N14A

and V

14-Lead Small Outline integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DS005985.prf

and V

0.2

Features

Schematic Diagram

Wide supply voltage range:

High noise immunity: 0.7 V

Low power TTL compatibility:

Fan out of 2 driving 74L or 1 driving 74LS

Hysteresis: 0.4 V

Equivalent to MM74C14

Equivalent to MC14584B

0.2 V

Package Description

guaranteed

(typ.),

October 1987

Revised January 1999

3V to 15V

(typ.)

www.fairchildsemi.com

Related parts for CD40106BCN_Q

CD40106BCN_Q Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View © 1999 Fairchild Semiconductor Corporation Features Wide supply voltage range: High noise immunity: 0.7 V Low power TTL compatibility: ...

Page 2

Absolute Maximum Ratings (Note 2) DC Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline ) Lead Temperature (T L (Soldering, 10 ...

Page 3

AC Electrical Characteristics pF, R 200k, t and t 20 ns, unless otherwise specified Symbol Parameter Propagation Delay Time from PHL PLH Input to Output t or ...

Page 4

Typical Performance Characteristics Typical Transfer Characteristics Guaranteed www.fairchildsemi.com Guaranteed Trip Point Range 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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