DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 4
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DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
DS32506/DS32508/DS32512
LIST OF FIGURES
Figure 2-1. Block Diagram ........................................................................................................................................... 7
Figure 3-1. 12-Port Unchannelized DS3/E3 Card ....................................................................................................... 8
Figure 4-1. External Connections, Internal Termination Enabled................................................................................ 9
Figure 4-2. External Connections, Internal Termination Disabled............................................................................. 10
Figure 8-1. DS3 Waveform Template ........................................................................................................................ 27
Figure 8-2. STS-1 Waveform Template..................................................................................................................... 28
Figure 8-3. E3 Waveform Template........................................................................................................................... 29
Figure 8-4. STS-1 and E3 Jitter Tolerance................................................................................................................ 34
Figure 8-5. DS3 Jitter Tolerance................................................................................................................................ 34
Figure 8-6. DS3 and E3 Wander Tolerance .............................................................................................................. 35
Figure 8-7. Jitter Attenuation/Jitter Transfer .............................................................................................................. 36
Figure 8-8. PRBS Synchronization State Diagram.................................................................................................... 38
Figure 8-9. Repetitive Pattern Synchronization State Diagram................................................................................. 39
Figure 8-10. SPI Clock Polarity and Phase Options.................................................................................................. 45
Figure 8-11. SPI Bus Transactions............................................................................................................................ 46
Figure 8-12. Interrupt Signal Flow ............................................................................................................................. 47
Figure 11-1. Transmitter Framer Interface Timing Diagram...................................................................................... 95
Figure 11-2. Receiver Framer Interface Timing Diagram .......................................................................................... 95
Figure 11-3. Parallel CPU Interface Intel Read Timing Diagram (Nonmultiplexed) .................................................. 99
Figure 11-4. Parallel CPU Interface Intel Write Timing Diagram (Nonmultiplexed) .................................................. 99
Figure 11-5. Parallel CPU Interface Motorola Read Timing Diagram (Nonmultiplexed) ......................................... 100
Figure 11-6. Parallel CPU Interface Motorola Write Timing Diagram (Nonmultiplexed) ......................................... 100
Figure 11-7. Parallel CPU Interface Intel Read Timing Diagram (Multiplexed) ....................................................... 101
Figure 11-8. Parallel CPU Interface Intel Write Timing Diagram (Multiplexed) ....................................................... 101
Figure 11-9. Parallel CPU Interface Motorola Read Timing Diagram (Multiplexed)................................................ 102
Figure 11-10. Parallel CPU Interface Motorola Write Timing Diagram (Multiplexed).............................................. 102
Figure 11-11. SPI Interface Timing Diagram ........................................................................................................... 104
Figure 11-12. JTAG Timing Diagram....................................................................................................................... 105
Figure 12-1. DS32512 Pin Assignment, Hardware and Microprocessor Interfaces................................................ 109
Figure 12-2. DS32512 Pin Assignment, Hardware Interface Only .......................................................................... 111
Figure 12-3. DS32512 Pin Assignment, Microprocessor Interface Only ................................................................. 113
Figure 12-4. DS32508 Pin Assignment, Hardware and Microprocessor Interfaces................................................ 115
Figure 12-5. DS32508 Pin Assignment, Hardware Interface Only .......................................................................... 117
Figure 12-6. DS32508 Pin Assignment, Microprocessor Interface Only ................................................................. 119
Figure 12-7. DS32506 Pin Assignment, Hardware and Microprocessor Interfaces................................................ 121
Figure 12-8. DS32506 Pin Assignment, Hardware Interface Only .......................................................................... 123
Figure 12-9. DS32506 Pin Assignment, Microprocessor Interface Only ................................................................. 125
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