DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 86
![no-image](/images/no-image-200.jpg)
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 86 of 130
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: BERT Seed/Pattern (BSP[15:0])
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 15 to 0: BERT Seed/Pattern (BSP[31:16])
BERT Seed/Pattern (BSP[31:0]). This 32-bit field is the programmable seed for a transmit PRBS pattern, or the
programmable pattern for a transmit or receive repetitive pattern. BSP[31] is the first bit output on the transmit side
for a 32-bit repetitive pattern or 32-bit PRBS. BSP[31] is the first bit input on the receive side for a 32-bit repetitive
pattern. See Section 8.5.1.
15
15
0
7
0
0
7
0
14
14
0
6
0
0
6
0
BERT.SPR1
BERT Seed/Pattern Register #1
n * 80h + 54h
BERT.SPR2
BERT Seed/Pattern Register #2
n * 80h + 56h
13
13
0
5
0
0
5
0
86 of 130
12
12
0
4
0
0
4
0
BSP[31:24]
BSP[23:16]
BSP[15:8]
BSP[7:0]
11
11
0
3
0
0
3
0
10
10
0
2
0
0
2
0
DS32506/DS32508/DS32512
9
0
1
0
9
0
1
0
8
0
0
0
8
0
0
0
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