DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 78
![no-image](/images/no-image-200.jpg)
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 78 of 130
- Download datasheet (2Mb)
Bit 0: Analog Loss Of Signal Interrupt Enable (ALOSIE). This bit is the interrupt enable for the LIU.SRL:ALOSL
bit.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bits 7 to 0: Receive Gain Level (RGL[7:0]). This field reports the real-time receiver gain level in 0.25 dB
increments. Values of 00–60h indicate receiver gain of 0dB to +24dB in 0.25dB increments. Values of F4–Fifth
indicate receiver gain of -3dB to -0.25dB in 0.25dB increments. See Section 8.3.3.
0 = interrupt disabled
1 = interrupt enabled
RGL7
15
—
0
7
0
RGL6
14
—
0
6
0
LIU.RGLR
LIU Receive Gain Level Register
n * 80h + 2Eh
RGL5
13
—
0
5
0
RGL4
78 of 130
12
—
0
4
0
RGL3
11
—
0
3
0
RGL2
10
—
0
2
0
DS32506/DS32508/DS32512
RGL1
—
9
0
1
0
RGL0
—
8
0
0
0
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