DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 64
![no-image](/images/no-image-200.jpg)
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 64 of 130
- Download datasheet (2Mb)
Bits 7 and 6: LIU Mode (LM[1:0]). These bits select the operating mode of the port. See Section 8.1.
Bit 4: Receive Output Disable (ROD). See Section 8.3.6.4.
Bit 3: Transmit Binary Interface Enable (TBIN). See Section 8.2.2.
Bit 2: Receive Binary Interface Enable (RBIN). See Section 8.3.6.
Bit 1: Transmit Common Clock Mode (TCC). See Section 8.2.1.1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
00 = DS3
01 = E3
10 = STS-1
11 = reserved
0 = enable the receiver outputs
1 = disable the receiver outputs (RCLK, RPOS/RDAT, and RNEG/RLCV)
0 = Transmitter framer interface is bipolar on the TPOS and TNEG pins. The B3ZS/HDB3 encoder
1 = Transmitter framer interface is binary on the TDAT pin. The B3ZS/HDB3 encoder is enabled.
0 = Receiver framer interface is bipolar on the RPOS and RNEG pins. The B3ZS/HDB3 decoder is
1 = Receiver framer interface is binary on the RDAT pin with the RLCV pin indicating line-code
0 = Source transmit clock for port n from
1 = Source transmit clock for port n from TCLK1
is disabled.
disabled.
violations. The B3ZS/HDB3 encoder is enabled.
15
—
0
7
0
LM[1:0]
14
—
0
0
6
PORT.CR2
Port Control Register 2
n * 80h + 02h
13
—
—
0
5
0
TCLKn
64 of 130
ROD
12
—
0
4
0
TBIN
11
—
0
3
0
RBIN
10
—
0
2
0
DS32506/DS32508/DS32512
TCC
—
9
0
1
0
—
—
8
0
0
0
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