DS32508N-W Maxim Integrated, DS32508N-W Datasheet - Page 63
![no-image](/images/no-image-200.jpg)
DS32508N-W
Manufacturer Part Number
DS32508N-W
Description
Network Controller & Processor ICs
Manufacturer
Maxim Integrated
Datasheet
1.DS32512W.pdf
(130 pages)
Specifications of DS32508N-W
Part # Aliases
90-32508-NW0
- Current page: 63 of 130
- Download datasheet (2Mb)
Bit 3: Transmit Power-Down (TPD). When this bit is set, the transmit path of the port is powered down and
considered “out of service”. The digital logic is powered down by stopping the clocks. See Section 8.11.
Bit 2: Receive Power-Down (RPD). When this bit is set, the receive path of the port is powered down and
considered “out of service”. The digital logic is powered down by stopping the clocks. See Section 8.11.
Bit 1: Reset Data Path (RSTDP). When this bit is set, it forces all of the port’s internal data path and status
registers to their default state. This bit must be set high for a minimum of 100ns and then set back low. See Section
8.11.
Bit 0: Reset (RST). When this bit is set, all of the internal data path and status and control registers (except this
RST bit) of this port are reset to their default state. This bit must be set high for a minimum of 100ns. This bit is
logically ORed with the inverted hardware signal
0 = Normal operation
1 = Power down the port transmit path
0 = Normal operation
1 = Power down the port receive path (RPOS/RDAT, RNEG/RLCV, and
0 = Normal operation
1 = Force all data path registers to their default values
0 = Normal operation
1 = Force all internal registers to their default values
(TXP
RST
and
63 of 130
and the GLOBAL.CR1:RST bit. See Section 8.11.
TXN
become high impedance)
RCLK
DS32506/DS32508/DS32512
become high impedance)
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