IS42S16100E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TL Datasheet - Page 13

• Manufacturer Part Number: IS42S16100E-7TL
• Description: IC SDRAM 16MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1071; IS42S16100E-7TL

IS42S16100E, IC42S16100E
Self-Refresh Command
(CS, RAS, CAS, CKE = LOW, WE = HIGH)
This command executes the self-refresh operation. The
row address to be refreshed, the bank, and the refresh
interval are generated automatically internally during this
operation. The self-refresh operation is started by dropping
the CKE pin from HIGH to LOW. The self-refresh operation
continues as long as the CKE pin remains LOW and there
is no need for external control of any other pins. The
self-refresh operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the device internal recovery period (t
has elapsed. After the self-refresh, since it is impossible
to determine the address of the last row to be refreshed,
an auto-refresh should immediately be performed for all
addresses (4096 cycles).
Both banks must be placed in the idle state before executing
this command.
Burst Stop Command
(CS, WE, = LOW, RAS, CAS = HIGH)
The command forcibly terminates burst read and write
operations. When this command is executed during a
burst read operation, data output stops after the CAS
latency period has elapsed.
No Operation
(CS, = LOW, RAS, CAS, WE = HIGH)
This command has no effect on the device.
Device Deselect Command
(CS = HIGH)
This command does not select the device for an object of
operation. In other words, it performs no operation with
respect to the device.
Integrated Silicon Solution, Inc. — www.issi.com
Rev. C
01/22/08
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Power-Down Command
(CKE = LOW)
When both banks are in the idle (inactive) state, or when
at least one of the banks is not in the idle (inactive) state,
this command can be used to suppress device power
dissipation by reducing device internal operations to
the absolute minimum. Power-down mode is started by
dropping the CKE pin from HIGH to LOW. Power-down
mode continues as long as the CKE pin is held low. All
pins other than the CKE pin are invalid and none of the
other commands can be executed in this mode. The
power-down operation is terminated by raising the CKE
pin from LOW to HIGH. The next command cannot be
executed until the recovery period (t
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (t
the maximum time that power-down mode can be held
is just under the refresh cycle time.
Clock Suspend
(CKE = LOW)
This command can be used to stop the device internal clock
temporarily during a read or write cycle. Clock suspend
mode is started by dropping the CKE pin from HIGH to
LOW. Clock suspend mode continues as long as the
CKE pin is held LOW. All input pins other than the CKE
pin are invalid and none of the other commands can be
executed in this mode. Also note that the device internal
state is maintained. Clock suspend mode is terminated
by raising the CKE pin from LOW to HIGH, at which point
device operation restarts. The next command cannot be
executed until the recovery period (t
Since this command differs from the self-refresh command
described above in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (t
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
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