IS42S16100E-7TL ISSI, Integrated Silicon Solution Inc, IS42S16100E-7TL Datasheet - Page 36

• Manufacturer Part Number: IS42S16100E-7TL
• Description: IC SDRAM 16MBIT 143MHZ 50TSOP
• Manufacturer: ISSI, Integrated Silicon Solution Inc
• Type: SDRAMr

Specifications of IS42S16100E-7TL

• Format - Memory: RAM
• Memory Type: SDRAM
• Memory Size: 16M (1M x 16)
• Speed: 143MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 50-TSOPII
• Organization: 1Mx16
• Density: 16Mb
• Address Bus: 12b
• Access Time (max): 6/5.5ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 130mA
• Pin Count: 50
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 706-1071; IS42S16100E-7TL

IS42S16100E, IC42S16100E
Bank Active Command Interval
When the selected bank is precharged, the period trp
has elapsed and the bank has entered the idle state,
the bank can be activated by executing the active
command. If the other bank is in the idle state at that
time, the active command can be executed for that bank
after the period t
banks will be in the active state. When a bank active
command has been executed, a precharge command
must be executed for
Clock Suspend
When the CKE pin is dropped from HIGH to LOW during
a read or write cycle, the IS42S16100E/IC42S16100E
enters clock suspend mode on the next CLK rising edge.
This command reduces the device power dissipation by
stopping the device internal clock. Clock suspend mode
continues as long as the CKE pin remains low. In this
state, all inputs other than CKE pin are invalid and no
other commands can be executed. Also, the device internal
states are maintained. When the CKE pin goes from LOW
to HIGH clock suspend mode is terminated on the next
CLK rising edge and device operation resumes.
36
CAS latency = 3
CAS latency = 2, burstlength = 4
COMMAND
COMMAND
COMMAND
rrd
CLK
CLK
has elapsed. At that point both
CKE
CLK
BANK ACTIVE (BANK 0)
BANK ACTIVE (BANK 0)
DQ
ACT 0
ACT 0
READ (BANK 0)
READ 0
t
t
RRD
RCD
D
OUT
BANK ACTIVE (BANK 1)
BANK ACTIVE (BANK 0)
CLOCK SUSPEND
0
READ 0
ACT 1
that bank within the ACT to PRE command period (t
Also note that a precharge command cannot be executed
for an active bank before t
After a bank active command has been executed and
the trcd period has elapsed, read write (including auto-
precharge) commands can be executed for that bank.
The next command cannot be executed until the recovery
period (t
Since this command differs from the self-refresh command
described previously in that the refresh operation is not
performed automatically internally, the refresh operation
must be performed within the refresh period (tref). Thus
the maximum time that clock suspend mode can be held
is just under the refresh cycle time.
Integrated Silicon Solution, Inc. — www.issi.com
D
OUT
cka
) has elapsed.
1
D
OUT
ras
2
(min) has elapsed.
D
OUT
3
ras
01/22/08
max).
Rev. C