C8051F989-GUR Silicon Labs, C8051F989-GUR Datasheet - Page 138

• Manufacturer Part Number: C8051F989-GUR
• Description: 8-bit Microcontrollers - MCU 4kB 512B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F989-GUR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051F99x-C8051F98x
13.3. Interrupt Priorities
Each interrupt source can be individually programmed to one of two priority levels: low or high. A low
priority interrupt service routine can be preempted by a high priority interrupt. A high priority interrupt
cannot be preempted. If a high priority interrupt preempts a low priority interrupt, the low priority interrupt
will finish execution after the high priority interrupt completes. Each interrupt has an associated interrupt
priority bit in in the Interrupt Priority and Extended Interrupt Priority registers used to configure its priority
level. Low priority is the default.
If two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. If both
interrupts have the same priority level, a fixed priority order is used to arbitrate. See Table 13.1 on
page 139 to determine the fixed priority order used to arbitrate between simultaneously recognized
interrupts.
13.4. Interrupt Latency
Interrupt response time depends on the state of the CPU when the interrupt occurs. Pending interrupts are
sampled and priority decoded each system clock cycle. Therefore, the fastest possible response time is 7
system clock cycles: 1 clock cycle to detect the interrupt, 1 clock cycle to execute a single instruction, and
5 clock cycles to complete the LCALL to the ISR. If an interrupt is pending when a RETI is executed, a
single instruction is executed before an LCALL is made to service the pending interrupt. Therefore, the
maximum response time for an interrupt (when no other interrupt is currently being serviced or the new
interrupt is of greater priority) occurs when the CPU is performing an RETI instruction followed by a DIV as
the next instruction. In this case, the response time is 19 system clock cycles: 1 clock cycle to detect the
interrupt, 5 clock cycles to execute the RETI, 8 clock cycles to complete the DIV instruction and 5 clock
cycles to execute the LCALL to the ISR. If the CPU is executing an ISR for an interrupt with equal or higher
priority, the new interrupt will not be serviced until the current ISR completes, including the RETI and
following instruction.
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