C8051F989-GUR Silicon Labs, C8051F989-GUR Datasheet - Page 201

• Manufacturer Part Number: C8051F989-GUR
• Description: 8-bit Microcontrollers - MCU 4kB 512B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F989-GUR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

20.2. SmaRTClock Clocking Sources
The SmaRTClock peripheral is clocked from its own timebase, independent of the system clock. The
SmaRTClock timebase can be derived from an external CMOS clock, the internal LFO, or the SmaRT-
Clock oscillator circuit, which has two modes of operation: Crystal Mode, and Self-Oscillate Mode. The
oscillation frequency is 32.768 kHz in Crystal Mode and can be programmed in the range of 10 kHz to
40 kHz in Self-Oscillate Mode. The internal LFO frequency is 16.4 kHz ±20%. The frequency of the
SmaRTClock oscillator can be measured with respect to another oscillator using an on-chip timer. See
Section “25. Timers” on page 276 for more information on how this can be accomplished.
Note: The SmaRTClock timebase can be selected as the system clock and routed to a port pin. See Section
20.2.1. Using the SmaRTClock Oscillator with a Crystal or External CMOS Clock
When using Crystal Mode, a 32.768 kHz crystal should be connected between XTAL3 and XTAL4. No
other external components are required. The following steps show how to start the SmaRTClock crystal
oscillator in software:
1. Configure the XTAL3 and XTAL4 pins for Analog I/O.
2. Set SmaRTClock to Crystal Mode (XMODE = 1).
3. Disable Automatic Gain Control (AGCEN) and enable Bias Doubling (BIASX2) for fast crystal startup.
4. Set the desired loading capacitance (RTC0XCF).
5. Enable power to the SmaRTClock oscillator circuit (RTC0EN = 1).
6. Wait 20 ms.
7. Poll the SmaRTClock Clock Valid Bit (CLKVLD) until the crystal oscillator stabilizes.
8. Poll the SmaRTClock Load Capacitance Ready Bit (LOADRDY) until the load capacitance reaches its
9. Enable Automatic Gain Control (AGCEN) and disable Bias Doubling (BIASX2) for maximum power
10.Enable the SmaRTClock missing clock detector.
11. Wait 2 ms.
12.Clear the PMU0CF wake-up source flags.
In Crystal Mode, the SmaRTClock oscillator may be driven by an external CMOS clock. The CMOS clock
should be applied to XTAL3. XTAL34 should be left floating. In this mode, the external CMOS clock is ac
coupled into the SmaRTClock and should have a minimum voltage swing of 400 mV. The CMOS clock sig-
nal voltage should not exceed VDD or drop below GND. Bias levels closer to VDD will result in lower I/O
power consumption because the XTAL3 pin has a built-in weak pull-up. The SmaRTClock oscillator should
be configured to its lowest bias setting with AGC disabled. The CLKVLD bit is indeterminate when using a
CMOS clock, however, the OSCFAIL bit may be checked 2 ms after SmaRTClock oscillator is powered on
to ensure that there is a valid clock on XTAL3.
programmed value.
savings.
“19. Clocking Sources” on page 186 for information on selecting the system clock source and Section “21. Port
Input/Output” on page 213 for information on how to route the system clock to a port pin. The SmaRTClock
timebase can also be routed to a port pin while the device is in its ultra low power sleep mode. See the
PMU0MD register description for details.
Rev. 1.1
C8051F99x-C8051F98x
201