C8051F989-GUR Silicon Labs, C8051F989-GUR Datasheet - Page 180

• Manufacturer Part Number: C8051F989-GUR
• Description: 8-bit Microcontrollers - MCU 4kB 512B RAM
• Manufacturer: Silicon Labs

Specifications of C8051F989-GUR

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Processor Series: C8051

C8051F99x-C8051F98x
18.1. Power-On Reset
During power-up, the device is held in a reset state and the RST pin voltage tracks V
pull-up) until the device is released from reset. After VDD settles above VPOR, a delay occurs before the
device is released from reset; the delay decreases as the V
defined as how fast V
timing. For valid ramp times (less than 3 ms), the power-on reset delay (T
1.8 V) or 15 ms (V
Note: The maximum V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000), software can
read the PORSF flag to determine if a power-up was the cause of reset. The contents of internal data
memory should be assumed to be undefined after a power-on reset.
The POR supply monitor can be disabled to save power by writing 1 to the MONDIS (PMU0MD.5) bit.
When the POR supply monitor is disabled, all reset sources will trigger a full POR and will re-enable the
POR supply monitor.
18.2. Power-Fail Reset
C8051F99x-C8051F98x devices have a V
source after each power-on or power-fail reset. When enabled and selected as a reset source, any power
down transition or power irregularity that causes V
driven low and the CIP-51 will be held in a reset state (see Figure 18.2). When V
above V
After a power-fail reset, the PORSF flag reads 1, the contents of RAM invalid, and the V
180
before
See specification
table for min/max
voltages.
RST
, the CIP-51 will be released from the reset state.
V
DD
reaches the V
Logic HIGH
DD
Logic LOW
DD
= 3.6 V).
DD
V
POR
ramp time is 3 ms; slower ramp times may cause the device to be released from reset
ramps from 0 V to V
Figure 18.2. Power-Fail Reset Timing Diagram
POR
RST
level.
Power-On
DD
Reset
POR
Supply Monitor that is enabled and selected as a reset
Rev. 1.1
). Figure 18.2 plots the power-on and V
T
PORDelay
DD
to drop below V
DD
ramp time increases (V
Power-On
RST
PORDelay
Reset
will cause the RST pin to be
) is typically 7 ms (V
T
PORDelay
DD
DD
DD
returns to a level
DD
(through a weak
DD
supply monitor
VDD
monitor reset
ramp time is
t
DD
=